T2E-CAD: Linking Technology and Electronic System CAD
Chairman
Sani Nassif (IBM)
Overview
This workshop is organised by the IEEE Council on Electronic Design Automation (CEDA), with several leading experts in the TCAD field presenting both the methodology and case studies.
Location
Grand Central Hotel in Glasgow, Scotland, United Kingdom.
Programme
08:30
Registration & Gathering
Abstract
To comeSpeaker Biography
Dr Nassif received his Bachelors degree with Honors from the American University of Beirut in 1980, and his Masters and PhD degrees from Carnegie-Mellon University in 1981 and 1985 respectively. He then worked for ten years at Bell Laboratories in the general area of technology CAD, focusing on various aspects of design and technology coupling including device modeling, parameter extraction, worst case analysis, design optimization and circuit simulation.In January 1996, he joined the then newly formed IBM Austin Research Laboratory (ARL), which was founded with a specific focus on research for the support of IBM's Power computer systems. After ten years of management, he stepped down to focus on technical work again, and he is currently working on applying techniques developed in the VLSI-EDA area to IBM's Smarter Planet initiative.
Dr Nassif has authored numerous conference and journal publications, and delivered many tutorials at top conferences. He is an IEEE Fellow, a member of the IBM Academy of Technology, a member of the ACM and the AAAS, and an IBM master inventor with more than 50 patents. Dr Nassif represents IBM on the SRC Science Area Coordinating Committee for CAD and Test, and is the chair for the committee in 2012. He maintains strong ties with academia, and has participated in PhD committees for students from MIT, CMU, Univ. Minnesota, Univ. Texas Austin, UCSB, UCI, Univ. Glasgow, and Univ. Michigan.
Personal website
Keynote
Abstract
To comeSpeaker Biography
Now with more than 35 years of experience in the integrated circuit industry, Dr. Nagel earned his BS, MS, and PhD degrees at the University of California where he was the lead developer of the SPICE circuit simulation program. As a result, a cottage industry of SPICE simulation tools was launched that proved very valuable to industry.During his 20 year career at Bell Laboratories, Dr. Nagel lead or participated in the development of numerous circuit, process and device simulation tools as well as working on the assertion of patents and negotiation of patent licenses in the AT&T Intellectual Property Division.
As an independent consultant, Dr. Nagel comes with extensive experience as an expert witness as well as in other consulting work.
Personal website
10:00-10:30
Coffee Break
Linking Technology to Design
Abstract
To comeSpeaker Biography
To comeAbstract
To comeSpeaker Biography
To comeAbstract
To comeSpeaker Biography
Greg Taylor is an Intel Fellow and director of the Circuit Research Lab in Intel’s Corporate Technology Group. He is responsible for research on low power and high speed circuits, high speed signaling, and enabling design and circuit technologies within Intel.Taylor joined Intel in 1991 and has held several senior design engineering positions working on 10 generations of microprocessors including members of Intel’s Pentium® Pentium® II, Pentium® III, and Intel NetBurst® microarchitecture families. Prior to joining Intel, he worked as a principal engineer at Bipolar Integrated Technology.
Taylor is a Fellow of the Institute of Electrical and Electronics Engineers. He received his bachelor’s degree in computer and systems engineering in 1981 from Rensselaer Polytechnic Institute (RPI). He also received a master’s degree and doctorate in computer and systems engineering from RPI in 1983 and 1985, respectively. His graduate work was completed with the support of a Fellowship from the Fannie and John Hertz Foundation.
12:30-13:30
Lunch
Case Studies
Abstract
To comeSpeaker Biography
Professor Asen Asenov (FIEEE, FRSE) received his MSc degree in solid-state physics from Sofia University, Bulgaria in 1979 and a PhD degree in physics from The Bulgarian Academy of Science in 1989. He has ten years of industrial experience as a head of the Process and Device Modelling Group in the Institute of Microelectronics, Sofia, leading in 1986 the development of one of the first integrated process and device CMOS simulators IMPEDANCE. He was a Visiting Professor at the Physics Department of The Technical University of Munich, Germany from 1989 to 1991 before joining the Department of Electronics and Electrical Engineering at the University of Glasgow, serving as a Head of Department from 1999 to 2003.Professor Asenov is now the James Watt Professor in Electrical Engineering and the Leader of the Glasgow Device Modelling Group. He directs the development of 2D and 3D quantum mechanical, Monte Carlo and classical device simulators and their application in the design of advanced and novel CMOS devices and has more than 650 publications and more than 170 invited talks in the above areas. Professor Asenov is a founder and CEO of Gold Standard Simulations (GSS) Ltd. GSS is the leader in physical simulation of statistical variability, statistical compact model extraction and generation technology and statistical circuit simulation.
He is a fellow of the Royal Academy of Scotland, an IEEE Fellow, a member of the IEEE Electron Device Society Technology Computer-Aided Design Committee and of the BP Fellowship Committee. He is co-author of European Nanoelectronics Advisory Council (ENIAC) Strategic Research Agenda (SRA) and the 2011 edition of the ITRS. He acted on behave of EC as and reviewer of more than 15 EC projects and as an evaluator of several FP5, FP6 and FP7 calls. He has been a general chair, co-chair and TPC chair for many international conferences and workshops.
Personal website
14:50-15:20
Coffee Break
Abstract
To comeSpeaker Biography
To come16:00-16:40
Stat-CM: Statistical Compact Modeling — SiNW/HV/HEMT Examples
Xing Zhou (NTU Singapore)
Abstract
Compact models (CMs) have been bridging technologies (fabs) to circuit designs (fabless) over the past decades. While the figure of merit (FOM) of a given circuit performance is measured by SPICE circuit simulations, the corresponding technology is represented by the CM parameters extracted from a “golden die” and the technology variations are given by the CM parameter statistical distributions. With technology scaling into the nanometer regime, while variations not being scaled correspondingly, statistical variability becomes a major show-stopper for continued scaling with sufficient design margins and yield. Conventional approach to circuit design with a nominal CM from a golden die while checking variations afterwards by corner models or Monte Carlo may not be able to meet the increasing demands for performance and yield.A truly scalable CM with a small number of physical parameters can capture transistor behaviors for a given technology. Its parametric distributions are built into the scalable model and can be used statistically (“stat-CM”). In this talk, we present ideas of using a scalable CM in variation/mismatch studies, compared with Monte Carlo and analytical formulations, on some transistor and simple logic-gate FOMs, using silicon nanowire (SiNW), high-voltage (HV), and high electron-mobility transistors (HEMT) as examples. The stat-CM approach can be generalized for bridging technology variations to multilevel modeling of transistor/circuits/gates/cells/blocks.
Speaker Biography
Dr. Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively. He has been with the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore, since he joined NTU in 1992.His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development. His recent research mainly focuses on nanoscale CMOS compact model development. His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs.
He has given more than 100 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions. He has been invited for visiting several universities, including Stanford University (1997 and 2001), Hiroshima University (2003), Universiti Teknologi Malaysia (2007), Fudan University (2011), and Tokyo Institute of Technology (2011 and 2012). He is the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference since 2002. Dr. Zhou is an elected member-at-large of the IEEE EDS Administrative Committee (AdCom/BoG) in 2004–2009 and 2010–2013, vice-president for Regions/Chapters in 2013, chair of the EDS Asia Pacific Subcommittee for Regions/Chapters in 2007–2012, and a member of the EDS Compact Modeling, Membership, Publications, and Educational Activities committees. He is a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices on compact modeling of emerging devices. He has been a senior member of IEEE since 1999, an EDS distinguished lecturer since 2000, and an editor for the IEEE Electron Device Letters since 2007.
Personal website