Abstract

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Abstract

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Speaker Biography

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Abstract

An overview is given of physical and electrical characterization of gate-oxide defects contributing to degradation of Field-Effect Transistors (FET). Interfacial dangling bond defects at the semiconductor/oxide interfaces are characterized electrically and compared to the electron spin resonance data. It is found that additional silicon dangling bonds (Pb0-ceters) acting as amphoteric interface traps are generated upon oxygen scavenging anneal. A close density of Pb0 centers is also found in Si/SiGe/Si/HfO₂ stacks, indicating efficient passivation of SiGe channel by a Si capping layer. The Ge dangling bond defects (Ge Pb1 centers) found at interfaces of SiGe with thermal SiO₂ are shown to behave as acceptor centers. Density of these defects is significantly influenced by compressive strain, which is developed in the SiGe during the Ge condensation annealing. Correlated with the strain, the efficiency of passivation of Ge Pb1 centers by molecular hydrogen is found to decrease, resulting in a high density of electrically active acceptor traps.

The Time-Dependent Defect Spectroscopy (TDDS) is an electrical characterization technique allowing the extraction of properties of individual gate-oxide defects in FETs. The primary properties of a defect are its capture and emission time constants, both dependent on the local electric gate field and the temperature. Considering the wide distributions of these defect properties, complete characterization of hundreds of defects is required over the full gate and drain voltage range from 0 to V_DD and also at different temperatures. This is desirable in order to model degradation for large, “analog” FETs and to model the ΔV_th-variability of deeply-scaled FETs.

Finally, the impact of individual charged defects on transistor properties is discussed. It is shown that the shift in the threshold voltage is exponentially distributed, with a small fraction of defects causing significant shifts of tens of mV. The average impact per charged defect is experimentally shown to be increasing with the gate oxide thickness, the substrate doping, and with the decreasing FET area. The average impact per charged defect is found to be reduced in SiGe substrates, contributing to lower degradation of SiGe-based FETs. In low-doped substrates, other sources of variability, such as interface states, are shown to take over. The impact of a single charged gate-oxide defect on the full I-V characteristic is measured and corroborated by atomistic device simulations, thus enabling the path to compact modeling of degraded deeply-scaled FET devices.

Speaker Biography

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Abstract

Al-Moatasem El-Sayed¹, Sanliang Ling¹, Matthew Watkins¹, Samuel Bradley^1,2 and Alexander Shluger<sup>1

1</sup>Department of Physics and Astronomy and London Centre for Nanotechnology, University College London, Gower Street, London WC1E 6BT, UK
²Department of Chemistry, University College London, Gordon Street, London WC1H 0AJ, UK

Capture and emission of carriers by point defects in gate dielectrics, such as SiO₂ and HfO₂, and at their interfaces with the substrate is thought to be responsible for the performance and reliability issues in MOS devices, in particular, 1/f noise, negative bias temperature instability (NBTI), and long-term dielectric reliability and degradation. Ultra-thin silicon dioxide layer present at the interface between Si and high-k films plays a critical role in the performance of high-k gate oxide stacks. However, detailed atomistic models relating device electrical characteristics to the properties of defects in gate dielectrics are only starting to emerge.

We review some of the theoretical models proposed for oxygen deficient defects in silica and hafnia and their charge trapping behaviour in relation to physical characterization of degradation processes in CMOS devices. Using several examples of interfaces, such as SiO₂/Si(001) and HfO₂/Pt(001), we will demonstrate how ab initio calculations can help to predict the rates of electron trapping/detrapping in SiO₂ films as well as the charge states of defects at different positions in the oxide with respect to the interface. We characterised the structure, stability and electronic properties of the interface and explore different mechanisms for oxygen diffusion near the Pt electrode to provide insight into the role of the electrode in HfO₂ based ReRAM devices.

Acknowledgments: The authors would like to thank EPSRC, FP7 project MORDRED, the Leverhulme Trust and Sematech for funding. We are grateful to K. P. McKenna and F. Lopez Gejo for useful discussions and help in calculations.

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Abstract

Asen Asenov^1,2, Salvatore M. Amoroso¹ and Louis Gerrer<sup>1

1</sup>Device Modelling Group, School of Engineering, University of Glasgow, Glasgow, G12 8LT, Scotland
²Gold Standard Simulations Ltd., The Rankine Building, Oakfield Avenue, Glasgow, G12 8LT, Scotland

Statistical variability and reliability introduced by the discreteness of charge and granularity of matter has become one of the most acute problems in CMOS scaling and Integration. In this talk we will present recent advances in the simulation of reliability associated with discrete charge trapping in advanced CMOS devices and circuits. The simulation techniques will cover drift-diffusion and Monte Carlo. The trapping and de-trapping dynamics will be handled by Kinetic Monte Carlo simulations techniques. The emphasis will be on the static and dynamic interaction of discrete trapped charges with different variability sources such as random discrete dopants, line edge roughness, polysilicon and metal gate granularity. Examples of statistical reliability simulation in conventional and novel CMOS transistors will be presented. The examples will cover bulk and FD SOI MOSFETs and FinFETs.

Speaker Biography

Professor Asen Asenov (FIEEE, FRSE) received his MSc degree in solid-state physics from Sofia University, Bulgaria in 1979 and a PhD degree in physics from The Bulgarian Academy of Science in 1989. He has ten years of industrial experience as a head of the Process and Device Modelling Group in the Institute of Microelectronics, Sofia, leading in 1986 the development of one of the first integrated process and device CMOS simulators IMPEDANCE. He was a Visiting Professor at the Physics Department of The Technical University of Munich, Germany from 1989 to 1991 before joining the Department of Electronics and Electrical Engineering at the University of Glasgow, serving as a Head of Department from 1999 to 2003.

Professor Asenov is now the James Watt Professor in Electrical Engineering and the Leader of the Glasgow Device Modelling Group. He directs the development of 2D and 3D quantum mechanical, Monte Carlo and classical device simulators and their application in the design of advanced and novel CMOS devices and has more than 650 publications and more than 170 invited talks in the above areas. Professor Asenov is a founder and CEO of Gold Standard Simulations (GSS) Ltd. GSS is the leader in physical simulation of statistical variability, statistical compact model extraction and generation technology and statistical circuit simulation.

He is a fellow of the Royal Academy of Scotland, an IEEE Fellow, a member of the IEEE Electron Device Society Technology Computer-Aided Design Committee and of the BP Fellowship Committee. He is co-author of European Nanoelectronics Advisory Council (ENIAC) Strategic Research Agenda (SRA) and the 2011 edition of the ITRS. He acted on behave of EC as and reviewer of more than 15 EC projects and as an evaluator of several FP5, FP6 and FP7 calls. He has been a general chair, co-chair and TPC chair for many international conferences and workshops.

Personal website

Abstract

Franz Schanovsky¹, Wolfgang Gös¹ and Tibor Grasser<sup>1

1</sup>Institute for Microelectronics, TU Wien, Austria

Several reliability issues in MOS transistors - such as the bias temperature instability, hot-carrier degradation, and gate leakage - have been traced back to the capture and emission of carriers at point-defects in the oxide. The trapping behavior of these defects depends on the device temperature and the oxide field in a highly non-trivial manner. Detailed capture and emission time constants of single defects have recently been obtained from time-dependent defect spectroscopy (TDDS) measurements. The complex behavior of these time constants is most accurately explained using a multi-state multi-phonon model. In this model, the defects capture and emit carriers through a non-radiative multi-phonon process. Additionally, each defect has (at least) two internal states where each internal state gives rise to different trapping dynamics.

The purpose of this talk is to introduce the multi-state multi-phonon defect model to scientists working in the field of semiconductor device simulation. We give a brief and intuitive introduction to the theory of non-radiative multi-phonon capture and emission at oxide defects in MOS structures. The relation of the multi-phonon description to the classical Shockley-Read-Hall model, which is usually employed in semiconductor device simulation, is discussed. The additional complexity of multiple internal defect states is justified based on experimental data obtained from TDDS measurements. The microphysical nature of these internal states is explained on the basis of atomistic defect models.

Speaker Biography

Tibor Grasser received his Ph.D. degree in technical sciences from the TU Wien where he is currently employed as an Associate Professor. In 2003 he was appointed director of the Christian Doppler Laboratory for TCAD in Microelectronics. Dr. Grasser is the co-author or author of more than 400 scientific articles, editor of a book on advanced device simulation, a distinguished lecturer of the IEEE Electron Devices Society, a senior member of IEEE, has been involved in various functions of outstanding conferences such as IEDM, IRPS, SISPAD, IWCE, ESSDERC, IIRW, and ISDRS, is a recipient of the Best Paper Awards at IRPS (2008, 2010, and 2012), ESREF (2008) and the IEEE EDS Paul Rappaport Award (2011). He was also a chairman of SISPAD 2007 and is currently TPC chair of IIRW 2013.

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Abstract

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Abstract

With relentless scaling of physical dimensions and proliferation of complex multi-component stacks for gate dielectric applications, well-established phenomenological descriptions, which dominate in the reliability modeling field, are losing their predictive capability. There is a growing need to complement the conventional statistical approach with the microscopic, physics-based degradation models, which would explicitly take into consideration atomic-level material properties and inter-material interactions.

Within the microscopic description, stress-induced defect generation at any location is driven by the local electric field and temperature, which, in turn, are determined by a distribution of the defects generated during a given stress period throughout the entire device region. Therefore, the degradation process is essentially non-local and probabilistic in nature and cannot be comprehensibly described by the analytical compact models. Developing a simplified compact model, which would retain all major features of the non-local Monte Carlo description, presents a challenging goal.

Simulating degradation processes by employing atomic characteristics of the electrically active defects allows device reliability to be connected to the specifics of the gate stack and substrate structures, thus providing a helpful feedback to process optimization. In this presentation, we discuss limitations of the traditional description and provide examples of the implementation of a microscopic approach for reliability evaluation.

Speaker Biography

Gennadi Bersuker has been working at SEMATECH on electrical and physical characterization of the frond end processes, most recently the planar and 3D high-k devices, advanced memory, and III-V logic devices. He is the Chair of Reliability Physics EDS committee, an Editor of IEEE Transactions on Device Materials and Reliability and has been involved in organizing, chairing, or serving as a committee member in a number of technical conferences, including IRW, IRPS, IEDM, APS, etc. He is a SEMATECH Fellow and has published over 300 papers on the electronic properties of dielectrics and semiconductor processing and reliability.