Abstract
Title: Statistical Reliability Modeling and Characterization in Scaled CMOS Design
The scaling of CMOS technology to sub-45nm nodes inevitability leads to multiple reliability concerns, such as positive/negative-bias-temperature-instability (PBTI/NBTI), channel-hot-carrier (CHC), random telegraph noise (RTN), and dielectric breakdown in both transistors and interconnect. While traditional research in this area has focused only on technology improvement, ignoring these effects in the design process causes an excessive amount of over-margining.
Design for reliability requires predictive tools that comprehend the key degradation mechanisms, diagnose their impact on different performance metrics, and develop a prognostics solution. The situation is compounded with statistical interactions with process variability and dynamic circuit operations. To resolve these issues, this talk presents statistical reliability models at the device and circuit levels, as well as in-situ characterization techniques. Specific topics include: statistical correlation between reliability and variability, reliability degradation under low power operations, and on-chip test structure to directly sample circuit aging. These new models are well calibrated with silicon data, supporting design practices on reliability. This talk will end with a discussion on future promises and needs, illustrating the diverse opportunities of resilient design.
Bios
Dr. Yu (Kevin) Cao received the B.S. degree in physics from Peking University in 1996. He received the M.A. degree in biophysics and the Ph.D. degree in electrical engineering from University of California, Berkeley, in 1999 and 2002, respectively. He joined Arizona State University in 2004 where he is now Associate Professor of Electrical Engineering. He has published more than 140 articles and coauthored one book. His research interests include physical modeling of nanoscale technologies, design solutions for variability and reliability, and reliable integration of post-silicon technologies. Dr. Cao received the 2009 ACM SIGDA Outstanding New Faculty Award, 2007 Best Paper Award at ISLPED, the 2006 NSF CAREER Award, the 2006 and 2007 IBM Faculty Award, the 2004 Best Paper Award at ISQED, and the 2000 Beatrice Winner Award at ISSCC. He has served on numerous technical program committees and is a member of the IEEE EDS Compact Modeling Technical Committee.