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Toshiro Hiramoto

Abstract

Title: Measurements and characterization of statistical variability
 
The increasing variability in scaled transistors is one of the most critical problems in future VLSI. We have fabricated and measured large scale device-matrix-array (DMA) TEG of 1M transistors and 16k SRAM cells. In the first half of the talk, the origins of random drain current variability is discussed based on measured data and simulation. It is pointed out that the current variability is caused by not only Vth and gm variability but also “current-onset voltage” variability. In the second half, the relationship between measured static noise margin (SNM) and Vth of individual transistor in SRAM cells is discussed. It is found that the SNM variability is not explained by measured Vth variability alone.
 

Bios

Toshiro Hiramoto received B.S., M.S., and Ph.D degrees in electronicengineering from the University of Tokyo in 1984, 1986, and 1989,respectively. In 1989, he joined Device Development Center, Hitachi Ltd., Ome, Japan. In 1994, he joined Institute of Industrial Science, University of Tokyo, Japan, as an Associate Professor and has been a Professor since 2002. His research interests include low power CMOS devices design, variability, silicon nanowire transistors, and silicon single electron transistors. Dr. Hiramoto is a member of IEEE, IEICE, and JSAP. He was an Elected AdCom Member of IEEE EDS from 2001 to 2006. He served as the General Chair of Silicon Nanoelectronics Workshop in 2003 and the Program Chair in 1997, 1999, and 2001. He has served on Program Committee of Symposium on VLSI Technology since 2001. He was the Subcommittee Chair of CMOS Devices in 2005, the Asian Arrangement Co-Chair in 2006 and 2007, the Publications Chair in 2008, and the Emerging Technologies Chair in 2009 in IEDM.