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Asen Asenov

Abstract

Title: Interaction Between TCAD, Compact Models and Circuit Simulation to Support Statistical and Robust Design
 
Statistical variability, arising from the discreteness of charge and matter, poses increasing challenges to CMOS scaling and integration, and demands the introduction of statistical circuit and system design strategies and verification. It is very important to include accurate information about statistical variability associated with Random Discrete Dopants (RDD), Line Edge Roughness (LER), Poly Gate Granularity (PGG) and other dominant statistical variability sources in the preliminary design kit. Since at this stage the technology is not ready and the variability cannot be measured the statistical physical simulation of the MOSFET reliability becomes a necessity. Compact Models (CM) are the interface between technology and design and the statistical device variability that affects the circuit/system performance and yield must be accurately represented by the industry standard CM. Based on comprehensive statistical 3D simulation results of contemporary MOSFETs we compare different statistical CM parameter identification strategies for BSIM4 and PSP, providing critical information regarding their accuracy. Finally we illustrate the impact of different statistical compact model strategies on the accuracy of statistical circuit simulation.
 

Bios

Asen Asenov is a James Watt Professor in Electrical Engineering and a Leader of the Glasgow Device Modelling Group. He directs the development of 2D and 3D quantum mechanical, Monte Carlo and classical device simulators and their application in the design of advanced and novel CMOS devices. He has pioneered the simulations of statistical variability in nano-CMOS devices including random dopants, interface roughness and line edge roughness. He has over 530 publications and more than 160 invited talks in the above areas.

Andrew R. Brown

Abstract

Title: TCAD Simulation of Statistical Variability
 
It has become clear that the variability in transistor characteristics that was predicted by statistical TCAD simulations has now become a reality in current generation technologies. As devices scale to smaller dimensions it is no longer valid, when performing TCAD device simulations, to assume that doping profiles can be modelled as a continuous distribution, or that gate edges and oxide interfaces are perfectly straight. The discreteness of charges and the granularity of materials need to be accounted for. The Glasgow ‘atomistic’ device simulator has been developed for over 10 years to account for such effects and here we will look at how different sources of variability can be included in the TCAD simulations, leading to fully statistical simulations of MOSFET device characteristics. Potential sources of variability considered include discrete charges due to random discrete dopants and NBTI-induced trapped charges, line edge roughness in gate edges due to granularity in the photoresit, and poly-crystalline granularity in polysilicon and metal gates. The inclusion of quantum corrections using the density gradient method is also discussed.
 

Bios

Andrew R. Brown received the B.Eng (Hons) degree in Electronics and Electrical Engineering from the University of Glasgow in 1992. Since this time he has been a Research Associate in the Department of Electronics and Electrical Engineering at the University of Glasgow working on the development of parallel 3D simulators for semiconductor devices. He is lead developer of the Glasgow 3D ‘atomistic’ device simulator, designed to investigate intrinsic parameter fluctuations in nanometre scale MOSFETs due to random discrete doping, line edge roughness, oxide thickness variation and gate-stack non-uniformity. He is currently working on the European FP7 projects “Reliable and Variability tolerant System-on-a-chip Design in More-Moore Technologies (Reality)” and “Terascale Reliable Adaptive Memory Systems (Trams)”. Previous work includes the simulation of insulated gate bipolar transistors. His interests include high performance parallel computing, device modelling and 3D visualisation.
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