Technical Program:
Wednesday, September 6, 2000
Friday, September 8, 2000

Thursday, September 7

Session 2 - Devices: Advanced Transport Models

8:40 - 9:05

"Direct Solution of the Boltzmann Transport Equation in Nanoscale Si Devices"
K. Banoo, M. Lundstrom, and R.K. Smith*,
Purdue University, West Lafayette, IN and *Bell Laboratories, Lucent Technologies, Murray Hill, NJ
9:05 - 9:30
"Sub-Continuum Thermal Simulations of Deep Sub-micron Devices under ESD Conditions"
P.G. Sverdrup, K. Banerjee, Changhong Dai*, Wei-kai Shih*, R.W. Dutton, and K.E. Goodson,
Stanford University, Stanford, CA and *Intel Corporation
9:30 - 9:55
"Modeling and Simulation of Phonon Boundary Scattering in PDE-based Device Simulators"
O. Tornblad, P.G. Sverdrup, D. Yergeau, K.E. Goodson, Z. Yu, and R.W. Dutton,
Stanford University, Stanford, CA
Break (15 minutes)

10:10 - 10:35
"2-D Quantum Transport Device Modeling by Self-Consistent Solution of the Wigner and Poisson Equations"
Z. Han, N. Goldsman, and C-K Lin,
University of Maryland, College Park, MD
10:35 - 11:00
"Multi-Band Simulation of Interband Tunneling Devices Reflecting Realistic Band Structure"
M. Ogawa, R. Tominaga, and T. Miyoshi,
Kobe University, Kobe, Japan
11:00 - 11:25
"Electron Transport Properties in Novel Orthorhombically-strained Silicon Material Explored by the Monte Carlo Method"
X. Wang, D.L. Kencke, K.C. Liu, A.F. Tasch, Jr., L.F. Register and S.K Banerjee,
The University of Texas at Austin, Austin, TX
11:25 - 11:50
"Simulation of Gallium-Arsenide Based High Electron Mobility Transistors"
R. Quay, H. Massler, W. Kellner*, T. Grasser**, V. Palankovski**, and S. Selberherr**,
Fraunhofer Institute of Applied Solid-State Physics, Freiburg, Germany, *Infineon Technologies AG, Munich, Germany and **TU Vienna, Vienna, Austria

Session 3 - Interconnect Models and Numerical Techniques

8:30 - 9:05

Invited Speaker
"Generic Approaches to Parasitic Extraction Problems"
Joel Phillips, Cadence Berkeley Laboratories
9:05 - 9:30
"A Multi-Scale Random-Walk Thermal-Analysis Methodology for Complex IC-Interconnect Systems"
R.B. Iverson, Y.L. Le Coz, B. Kleveland*, and S. Wong*,
Rensselaer Polytechnic Institute, Troy, NY and *Stanford University, Stanford CA
9:30 - 9:55
"Extraction of (R, L, C, G) Interconnect Parameters in 2D Transmission Lines Using Fast and Efficient Numerical Tools"
F. Charlet, C. Bermond*, S. Putot, G. Le Carval, B. Fletchet*,
LETI, Grenoble, France and *LAHC, Universite de Savoie, Le Bourget du Lac, France
Break (15 minutes)

10:10 - 10:35
"Periodic Steady-State Analysis for Coupled Device and Circuit Simulation"
Y. Hu, and K. Mayaram,
Oregon State University, Corvallis, OR
10:35 - 11:00
"An Extracting Capacitance in a Stacked DRAM Cell by Numerical Method"
S. Yoon, O. Kwon, S. Yoon, and T. Won,
Inha University, Inchun, Korea
11:00 - 11:25
"An Exhaustive Method for Characterizing the Interconnect Capacitance Considering the Floating Dummy-Fills by Employing an Efficient Field Solving Algorithm"
J-K. Park, K-H Lee, J-H Lee, Y-K Park, and J-T Kong,
Samsung Electronics Co. Ltd., Kyungki-Do, Korea
11:25 - 11:50
"A Simulation System for Capacitance Variation by CMP Process Including Defocus Effect"
T. Ohta, M. Fujinaga, M. Kimura T. Wada, and K. Nishi,
Semiconductor Leading Edge Technologies, Inc., Kanagawa, Japan

Session 4 - Circuit Simulation Models

1:30 - 2:05

Invited Speaker
"Circuit Simulation Models for Coming MOSFET Generations"
Mitiko Miura-Mattausch, Hiroshima University
2:05 - 2:30
"Comprehensive Analytical Charge Control and I-V Model of Modern MOSFET's by Fully Comprising Quantum Mechanical Effects"
Y. Ma, L. Liu, L. Tian, Z. Yu*, and Z. Li,
Tsinghua University, Beijing, P.R. China and *Stanford University, Stanford, CA
2:30 - 2:55
"An Analysis of Program and Erase Operation for FC-SGT Flash Memory Cells"
M. Hioki, T. Endoh, H. Sakuraba, M. Lenski, and F. Masuoka,
Tohoku University, Sendai, Japan

Session 5 - Process and Equipment Models

1:40 - 2:05

"Di-interstitial Diffusivity and Migration Path Calculations Based on Tight-Binding Hamiltonian Molecular Dynamics"
M. Hane, T. Ikezawa, and G.H. Gilmer*,
NEC Corporation, Sagamihara, Japan and *Bell Laboratories, Lucent Technologies, Murray Hill, NJ
2:05 - 2:30
"CHAMPS (CHemicAL-Mechanical Planarization Simulator)"
Y-H Kim, K-J Yoo, K-H Kim, B-Y Yoon, Y-K Park, S-R Ha, and J-T Kong,
Samsung Electronics Co. Ltd., Kyungki-Do, Korea
2:30 - 2:55
"Integrated Simulation of Equipment and Topography for Plasma Etching in the DRM Reactor"
W-Y Chung, J-J Oh, T-K Kim, J-K Shin, K-I Seo*, Y-K Park, and J-T Kong,
Samsung Electronics Co., Kyunggi-Do, Korea and Sumsung Advanced Institute of Technology, Korea
3:00 - 6:30 Poster Session