2009 International Conference on Simulation of Semiconductor Process and Devices

September 9-11, 2009 • Hotel Del Coronado • San Diego • CA • USA

Conference Chair
Karti Mayaram
Oregon State University

Technical Committee Chair
Valery Axelrad
Sequoia Design Systems


Technical Committee Members:
A. Asenov, University of Glasgow
M. Duane, National Semiconductor
S. Dunham, University of Washington
K. Fukuda, Oki
N. Goldsman, University of Maryland
T. Grasser, TU Vienna
H. Jaouen, STMicroelectronics
E. Kan, Cornell University
J. Lorenz, Fraunhofer IISB
N. Mori, University of Osaka
C. Mouli, Micron
P. Oldiges, IBM
M. Orlowski, Virginia Tech
Y.-K. Park, Samsung
B. Polsky, Synopsys
M. Rudan, Universita di Bologna
Y.-M. Sheu, TSMC
K. Sonoda, Renesas
M. Stettler, Intel

Contact Information
Phone: (650)723-1349

Under the sponsorship of the Electron Devices Society of the IEEE, an international conference on the numerical modeling of semiconductor devices, processes and equipment for integrated circuits will be held in San Diego, California, USA from September 9-11, 2009.

This meeting provides an opportunity for the presentation and discussion of recent advances in modeling and simulation of semiconductor devices, processes and equipment for increased understanding and for applications to both design and manufacturing. The program consists of 20-minute presentations, with ample time for questions and answers. A poster session is also planned, which provides for a less formal venue and allows for more in-depth interactions with the authors. The presentations will be selected from two-page abstracts of topics which may include:

  • All aspects of device simulation, including transport in nano-structures and next generation devices such as Fin/tri-gate, UTSOI, and structures using non-conventional materials, effects of strain on carrier transport, models of device scaling limits, quantum effects, reliability, fluctuations, novel nano-scale devices such as QCA, SET, CNT, and molecular devices.
  • All aspects of front and back end process simulation, including both continuum and atomistic approaches, models for dopant activation and diffusion, oxidation, silicide growth, interface effects, effects due to stress, nano-scale fabrication, and design of new materials.
  • Equipment, topography, and lithography simulation. 
  • Virtual fab implementations and algorithms for computational lithography.
  • Interconnect modeling and algorithms including noise and parasitic effects.
  • Compact device modeling for circuit simulation, including high frequency and noise modeling.
  • Integration of circuit, device, process simulation with applications to performance modeling of circuits.
  • User interfaces and visualization.
  • High performance computing, advanced numerical methods and algorithms.
  • Mesh generation and adaptation.
  • Simulations of new memory structures such as nanocrystal, phase change, MRAM, and devices such as microsensors, microactuators, optoelectronics devices, lasers, and flat panel displays.
  • Process and device simulation for power generation, control and storage including photovoltaics, power devices, smart power, and other "green technologies".
  • Benchmarking, calibration, and verification of simulator models.


Deadline for submission of abstracts -- March 6, 2009

Two-page abstracts must be submitted by email to (PDF format only) and should include:
1.  Title of Paper
2.  Name, complete mailing address, and email of first author
3.  Names and affiliations of additional authors

Authors will be notified of the Technical Program Committee's decision by April 24, 2009.