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Workshop on Electromigration Reliability

Monday, September 24, 2007

This workshop is intended to provide a forum for the discussion and presentation of critical issues regarding electromigration reliability in on-chip metal interconnects. The downscaling of transistors in integrated circuits goes hand in hand with an introduction of new backend-of-line manufacturing process steps which results in new reliability challenges. Degradation phenomena in the interconnects include electromigration and stress-migration depending on the copper microstructure, adhesion between copper and surrounding materials, and residual process stresses.

Based on experimental and modeling work of leading experts in the field this workshop is aimed at understanding electromigration related phenomena critical for design and integration of future interconnect structures.

A tentative list of invited speakers is given below. The detailed workshop program will be announced soon. For more information on this SISPAD companion workshop please contact the workshop organizer directly:

Hajdin Ceric, TU Vienna, Austria
Siegfried Selberherr, TU Vienna, Austria

Schedule

09:00 - 09:05 Welcome
Hajdin Ceric
 
09:05 - 09:40 Introduction to the Electromigration Phenomenon in Integrated Circuit Metallization
J.J. Clement
Sandia National Laboratories (USA)
 
09:40 - 10:15 Extrapolation of Electromigration Failure Times
J.R. Lloyd
IBM (USA)
 
10:15 - 10:50 Void Dynamics in Cu Interconnects
C.V. Thompson
MIT (USA)
 
10:50 - 11:25 Electromigration in Flip Chip Solder Joints
K.N. Tu
UCLA (USA)
 
11:25 - 11:45 Coffee  
11:45 - 12:20 Physics Based Modeling of Electromigration-Induced Degredation Phenomena in Copper Interconnects
V. Sukharev
Ponte Solutions (USA)
 
12:20 - 12:55 Effect of Surface Treatments on the Electromigration Lifetime of Copper Wires
J. Gambino
IBM (USA)
 
12:55 - 13:30 Reliability Aspects of Copper Metallizations in Integrated Circuits
A. von Glasow
Infineon (Germany)
 
13:30 - 15:00 Lunch  
15:00 - 15:45 Geometry and Microstructure Effect on EM-Induced Copper Interconnect Degradation
E. Zschech and P. Ho
AMD (Germany) and University of Texas at Austin (USA)
 
15:45 - 16:20 Impact of New Interconnect Materials on Full-Chip Electromigration
C.L. Gan
Nanyang Technological University (Singapore)
 
16:20 - 16:55 A Comprehensive TCAD Approach for Assessing Electromigration Reliability of Modern Interconnects
H. Ceric
Institute for Microelectronics, TU Wien (Austria)
 

J. J. Clement, Sandia National Laboratories, USA

Introduction to the Electromigration Phenomenon in Integrated Circuit Metallization

Since being first identified as a failure mechanism in integrated circuits in the late 1960s, electromigration in thin-film metal conductors has been extensively studied. This introductory talk will describe basic mechanisms underlying the electromigration phenomenon. The historical development of electromigration models based on solutions to the one-dimensional continuity equation will be reviewed. Although rather simple, these models yield valuable insight to interpret experimental observations.

J. Joseph Clement received the B.S. degree in electrical engineering from the University of Notre Dame, Notre Dame, IN, and the M.S. and Ph.D degrees from Princeton University, Princeton, NJ. Upon completing his graduate work, he joined Sandia National Laboratories, Albuquerque, NM, working on radiation-hardened CMOS technology development. In 1985, he moved to Fairchild Semiconductor, Puyallup, WA, to do BiCMOS SRAM technology development. When Fairchild was sold to National Semiconductor in 1987, he went to Digital Equipment Corp., Hudson, MA. There he worked in several positions supporting four generations of CMOS technology development for VAX and Alpha microprocessors, until Digital semiconductor operations were sold to Intel in 1998. At that time he rejoined Sandia National Laboratories, where he now leads projects to assess vulnerabilities of critical electronic systems. top

 

J. R. Lloyd, IBM, USA

Extrapolation of Electromigration Failure Times

Extrapolation of electromigration lifetimes from accelerated testing to operational use conditions has historically been via the Black Equation t50 = A j-n exp(ΔH/kT). In this we have three parameters that must be determined experimentally, the current exponent, n, the activation energy, ΔH and a constant A. Theoretically, this can be justified for specific values of n and ΔH, but the general use of empirically generated values can be problematic. In addition, the assumption that the statistics of failure are identical at test and use conditions can be challenged if examined in detail. In this paper, the physics of electromigration failure will be applied to the use of Black’s Law considering both nucleation and growth of damage as well as non-Arrhenius temperature effects that are generally neglected. It will be seen that the naďve use of Black’s Law, as stated, and the assumption of constant statistics can result in predictions of lifetime that may be significantly in error. A scheme will be proposed to mitigate these errors enabling design rules to be generated that will ensure reliability but not unduly restrict performance.

Jim Lloyd is a Research Staff Member with IBM T.J. Watson Research Center in Yorktown Heights NY specializing in Reliability Science and Engineering. Prior to this, he had been with Jet Propulsion Laboratory, Digital Equipment Corporation and Max-Planck-Institut für Metallforschung in Stuttgart Germany following an earlier stint with IBM in East Fishkill NY. For several years he was also the proprietor of a consulting firm that had most of the leading IC manufacturers as clients. His work has centered about interconnect and interlevel dielectric reliability, specializing for many years in electromigration in Al and Cu based metallization. He has also taught thermodynamics and materials science at Stevens Institute of Technology and NY Polytechnic Institute and has been a guest lecturer at many universities throughout the world. He has published nearly 100 papers and book chapters in the professional literature and has served as a reviewer for many professional journals. top

 

C. V. Thompson, MIT, USA

Void Dynamics in Cu Interconnects

We have recently carried out in-situ scanning electron microscopy during electromigration testing of passivated Cu damascene interconnects, using top-down views that complement side-view studies carried out earlier by Zschech and co-workers. In both studies, voids were often observed to form at a distance (often many line-widths) away from the cathode via. These voids usually grew in place before drifting toward the cathode. We have also carried out post-testing backscattered electron diffraction analysis to correlate locations of void growth and variations in the rate and shape of drifting voids with grain structure features, including crystallographic texture. In addition, studies of the absolute and relative rates of void growth in unpassivated lines, also as a function of the crystallographic texture of the relevant grains in the lines, have been carried out. These studies have yielded values for the electromigration-induced diffusivity that allow prediction of void drift rates in passivated lines. These predictions are found to correlate well with observed drift rates. We have used experimentally-determined kinetic parameters with simple simulations of stress evolution, based on the Korhonen analysis, and conclude that the observation of voids at locations other than the cathode via indicates that these voids have grown from pre-existing voids or from defects that substantially reduce the barrier to void nucleation. Interconnect failure in the presence of such defects constitutes a fundamentally different failure mode from void nucleation and growth at the cathode, with a different, and more complex, dependence on the current density. Implications for scaling of test results to service conditions will be discussed.

Carl V. Thompson is the Stavros Salapatas Professor of Materials Science and Engineering in the Dept. of Materials Science and Engineering of the Massachusetts Institute of Technology. He has degrees in Materials Science and Engineering and Applied Physics from MIT and Harvard University, respectively, and has spent a year each as a visitor at Cambridge University in the Dept. of Materials Science and Metallurgy and at the Max Planck Institute for Metallurgy in Stuttgart. He is a past president of the Materials Research Society and currently chair’s the program for Advanced Materials for Micro- and Nanosystems in the Singapore-MIT Alliance. He has authored over 300 technical publications and edited 6 conference proceedings. His current research focuses on the structure, stability, and properties of thin films and nanostructures, as well as on growth mechanisms of nanowires and nanotubes. He and his students have carried out research on electromigration since the early 1980’s. top

 

K. N. Tu, UCLA, USA

Electromigration in Flip Chip Solder Joints

The demand of flip chip technology in high density packaging for advanced electronic consumer products is growing rapidly. Due to the decrease in device size and increase in current density, electromigration has now become the most serious reliability problem in flip chip solder joints, especially Pb-free solder joints. European Union Parliament has a directive to ban the use of Pb-based solders in consumer electronic products on July 1st, 2006. Hence there is an urgent need of R&D of Pb-free solders, including electromigration which has several unique features that are very different from the electromigration in Al and Cu interconnects. Solder alloy has a very small critical product of electromigration, thus it can fail at 103 A/cm2. Owing to the line-to-bump geometry in flip chip, current crowding occurs at the contact between the line and the bump and the failure mode of electromigration is a pancake-type void formation at the cathode. Eutectic solder composition has a constant chemical potential below the eutectic temperature, so it enables up-hill diffusion and a nearly complete phase separation to occur in electromigration without resistance. In this talk, the reliability issues of flip chip solder joints when electrical force is combined with either chemical force or mechanical force will also be discussed.

K. N. Tu received B.Sc., National Taiwan University; M.Sc., Brown University; Ph.D. in Applied Physics, Harvard University (1968). He spent 25 years at IBM T. J. Watson Research Center and served as Senior Manager of Materials Science Department before joining UCLA as professor in 1993. He was Science Research Council Senior Research Fellow and The Royal Society Guest Research Fellow at Cavendish Laboratory, UK, and received the Alexander von Humboldt Research Award for senior US scientists. He is a Fellow of American Physical Society; Fellow of the Metallurgical Society; Overseas Fellow of Churchill College, and served as President of the Materials Research Society in 1981. He received the Application to Practice Award of the Metallurgical Society in 1988 and TMS-EMPM Division Distinguished Scientist/Engineer Award in 2006. He is an academician of Academia Sinica, ROC. He has published over 440 journal papers and his number of citation is over 10000 and his h-factor is 56. He co-authored a textbook on “Electronic thin Film Science,” published by Macmillan in 1992, and authored a book on “Solder joint technology” to be published by Springer in June 2007. His research interests are in metal-silicon reactions, solder reactions, nanoscale reactions, polarity effect of electromigration on interfacial reactions, and kinetic theories of interfacial reactions. His website is www.seas.ucla.edu/eThinFilm/. top

 

V. Sukharev, Ponte Solutions, USA

Physics Based Modeling of Electromigration-Induced Degradation Phenomena in Copper Interconnects

The proposed talk will discuss a current status of our physics-based numerical simulations regarding the stress evolution during EM in dual-inlaid copper interconnect, and the capability to predict the sites for void nucleation and to describe a void movement and growth. Introduction of the copper grain orientation into the theoretical model together with the accurate calculation of stress generated by EM-induced plating allow us to develop a calculative model which is capable to predict a realistic pre-void stress relaxation caused by vacancy migration through all major diffusion venues such as interfaces and grain boundaries. Incorporation of the realistic textures obtained by EBSD analysis and consequent comparison of the simulations results with the SEM experiments allow us to validate the model predictability of the stress evolution in the studied via/line test structures during EM, and the particular voiding sites in the copper lines with real microstructures. The talk will discuss the theoretical study of voiding dynamics and the comparison of the obtained results with the in-situ SEM experiments as the next step toward understanding of the microstructure effect on interconnect degradation. We will demonstrate the effect of orientation dependency of activation energy of atomic transport along the GBs on the void growth and migration processes. It will be shown that a complete understanding of the texture effect on interconnect degradation becomes very important in the lines with strengthened interfaces. The target for further model development is the capability for providing recommendations for optimization of the copper deposition process, and making estimation of life-times of the interconnect lines characterized by different microstructures subjected to EM.

Valeriy Sukharev received the M.S. in solid-state physics from the Moscow Institute of Electrical Engineering, and the Ph.D. in physical chemistry from the Karpov Institute of Physical Chemistry in 1976 and 1983, respectively. He has held various academic positions at the Karpov Institute of Physical Chemistry, positions of visiting professor at Brown University and guest researcher at National Institute of Standards and Technology (NIST), working on the physical chemistry of heterogenious process. He has held senior technical positions at LSI Logic Advanced Development Lab working on modeling and simulating problems in microelectronics engineering. He joined Ponte Solutions, Inc. in 2005. He is author and coauthor of more than 100 scientific publications, one book and three book chapters, and a holder of several patents. His major research activity as a Chief Scientist of the Ponte R&D is related to development of new full-chip modeling and simulation capabilities for DFM applications. top

J. Gambino, IBM, USA

Effect of Surface Treatments on the Electromigration Lifetime of Copper Wires

It is well known that the fast diffusion path for copper wires during an electromigration stress is along the top interface between the copper and the dielectric capping layer. In this work, different surface treatments are performed prior to deposition of the dielectric capping layer and the effect on electromigration lifetime is discussed. The surface treatments that are studied include plasma precleans, gas cluster ion beam infusion, metal implants, and electroless CoWP deposition. Increased electromigration lifetimes are achieved when an “intermediate layer”, such as CuSiN, Ta-doped copper, or CoWP, is formed between the copper and the dielectric capping layer. The role of the intermediate layer in increasing the electromigration lifetime will be discussed.

Jeff Gambino received the B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and the Ph.D. degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984. He joined IBM, Hopewell Junction, NY, in 1984, where he worked on silicide processes for Bipolar and CMOS devices . In 1992, he joined the DRAM development alliance at IBM’s Advanced Semiconductor Technology Center, Hopewell Junction, NY. While there, he developed contact and interconnect processes for 0.25-, 0.175-, and 0.15-um DRAM products. In 1999, he joined IBM’s manufacturing organization in Essex Junction, VT, where he has worked on copper interconnect processes for CMOS logic and CMOS imager technology. He has published over 90 technical papers and holds over 100 patents. top

 

A. von Glasow, Infineon Technologies, Germany

Reliability Aspects of Copper Metallizations in Integrated Circuits

Since the transition from Aluminum to Copper as interconnect material of Integrated Circuits, a variety of different investigations have been performed to understand the behavior of the new metallization with regard to electromigration and stressmigration. While the degradation mechanisms for electromigration remained similar for both materials, the understanding of stressmigration in copper metallizations required more emphasis. Numerous publications were dedicated to this topic without fully revealing the nature of this phenomenon. This work presents the understanding of the degradation mechanism, describes the different phases of stressmigration, its dependency from process steps and geometrical variations and links the theory with experimental data. This knowledge enables the realization of optimized technology processes and circuit designs leading to optimum reliability.

Alexander von Glasow received the M.S. in electrical engineering 1995 from the Technical University of Munich, Germany. He has been working for the Reliability Methodology group of Infineon Technologies AG for eight years, published during this time more than 35 papers and holds more than 10 patents. His main focus was the qualification of copper metallizations and the development of appropriate assessment methodologies. In this field of work he received his PhD from the Technical University of Munich in 2006. Since 2003 he is in charge of the development of the 65nm technology platform at Infineon Technologies. top

 

E. Zschech, AMD, Germany

Geometry and Microstructure Effect on EM-induced Copper Interconnect Degradation

Statistical analysis of EM lifetimes of inlaid copper interconnects, in-situ microscopy experiments at embedded inlaid copper interconnect structures and numerical simulations of grain growth and EM degradation processes are necessary for future on-chip interconnect systems with a high immunity to EM-induced failures. This talk will review a long-term fruitful collaboration of scientists and engineers working in the field of experimental studies and simulations of EM processes. Experimental results, i. e. statistics of lifetime and void distributions, copper microstructure data from electron backscatter diffraction (EBSD) and X-ray diffraction (XRD) studies as well as in-situ scanning electron microscopy (SEM) and X-ray microscopy (XRM) studies of EM degradation processes will be discussed for dual-inlaid interconnect structures, varying geometry and process conditions. EM failure statistics for a large number of interconnects and in-situ studies for a selected number of samples, that allow to visualize the time-dependent evolution of voids, demonstrate that interconnect degradation and eventually interconnect failure depend on both interface bonding and copper microstructure. With decreasing interconnect dimensions, the copper microstructure will become more critical for interconnect reliability.

Ehrenfried Zschech is manager of the Center for Complex Analysis at AMD in Dresden, which he joined in 1997. His responsibilities include the analytical support for process control and technology development, as well as physical failure analysis. He received his diploma degree in solid-state physics and his Dr. rer. nat. degree from Dresden University of Technology. After having spent four years as a project leader in the field of metal physics and reliability of microelectronics interconnects at Research Institute of Non-Ferrous Metals in Freiberg, he was appointed as a university teacher for ceramic materials at Freiberg University of Technology. In 1992, he joined the development department at Airbus GmbH in Bremen. There he managed the metal physics group and worked on laser joining metallurgy of light metals. His current research interests are in the areas of thin film materials compatibility, structure and materials analysis and physical failure analysis in integrated circuit applications. He has published three books and more than 100 papers in scientific journals in the areas of solid-state physics and materials science. He is honorary professor for nanomaterials at the Brandenburg University of Technology in Cottbus, Germany. top

 

C. L. Gan, Nanyang Technological University, Singapore

Impact of New Interconnect Materials on Full-Chip Electromigration

In order to reduce the RC wiring delay, new materials have been continuously introduced into the interconnect technologies for the last few years. With Cu replacing Al as the interconnect material, various types of cap layer, such as SiO2, SiC, CoWP, has been investigated to reduce electromigration along the dominant Cu/cap interface. Furthermore, many types of inter-level dielectrics have been studied to give a lower dielectric constant. In this work, the effect of CoWP cap layer on the electromigration behaviour will be presented. The impact of such a new material on full-chip electromigration will be demonstrated through SysRel, a circuit-level reliability analysis tool. SysRel utilizes a hierarchical reliability analysis flow, with interconnect trees treated as the fundamental reliability unit.

Dr. Gan Chee Lip received his B.Eng (Electrical) from the National University of Singapore in 1999. He received his PhD in Advanced Materials for Micro- and Nano-Systems (AMM&NS) under the Singapore-MIT Alliance (SMA) Program in 2003. Dr Gan is currently an Assistant Professor in the School of Materials Science and Engineering, Nanyang Technological University, Singapore. He is concurrently a SMA Fellow in the AMM&NS under the Singapore-MIT Alliance Program. He is also in the executive committee of IEEE Reliability/CPMT/ED Chapter, Singapore. Dr. Gan’s current research interests include the reliability study of advanced interconnect systems, such as copper electromigration, time-dependent-dielectric-breakdown of low-k dielectrics and new assessment methodology for circuit level reliability projection. Another area of research is on the process integration and reliability of 3D interconnects through copper-copper wafer bonding. Research work is also carried out on the fabrication and reliability study of metallic nanowires by a template method as interconnects. top