Technical Program

Tuesday, September 9

Session 1: Plenary Session (CONVENTION HALL [HAKONE higashi+naka])
Chairpersons: K. Matsuzawa, Toshiba Corp.
　　　　　　　　　　　T. Grasser, Technical Univ. Vienna

9:20	Opening and Welcome Remarks K. Ishikawa, Renesas Technol. Corp.
9:30 1-1	Progress in Biosensor and Bioelectronics Simulations: New Applications for TCAD A. Hassibi², Y. Liu¹, and R.W. Dutton¹ ¹Stanford Univ. and ²Univ. of Texas, USA
10:15 1-2	Quasi-Ballistic Transport in Nanowire Field-Effect Transistors G. Baccarani, E. Gnani, A. Gnudi, and S. Reggiani Univ. Bologna, Itary
11:00 1-3	Understanding and Engineering of Carrier Transport in Advanced MOS Channels S. Takagi^1,2 ¹The Univ. Tokyo and ²MIRAI-AIST, Japan

11:45 Lunch

Session 2: Fluctuation (CONVENTION HALL [HAKONE higashi+naka])
Chairpersons: M. Ogawa, Kobe Univ.
　　　　　　　　　　　P. Oldiges, IBM

13:00 2-1	Computational Electronics in the 21^st Century: Challenges, Opportunities, Issues (Invited) M. Lundstrom Purdue Univ., USA
13:30 2-2	Full-band and Atomistic Simulation of n- and p-doped Double-gate MOSFETs for the 22nm Technology Node M. Luisier and G. Klimeck Purdue Univ., USA
13:50 2-3	Prediction of Random Dopant Induced Threshold Voltage Fluctuations in NanoCMOS Transistors D. Reid, C. Millar, G. Roy, S. Roy, R. Sinnott, G. Stewart, G. Stewart, and A. Asenov Univ. of Glasgow, UK
14:10 2-4	Impact of Fixed Charge at MOSFETs' SiO₂/Si Interface on V_th Variation A.T. Putra¹, T. Tsunomura², A. Nishida², S. Kamohara², K. Takeuchi², and T. Hiramoto^1,2 ¹Univ. of Tokyo and ²MIRAI-SELETE, Japan
14:30 2-5	Ensemble Monte Carlo/Molecular Dynamics Simulation of Electron Mobility in Silicon with Ordered Dopant Arrays T. Terunuma¹, T. Watanabe¹, T. Shinada¹, Y. Kamakura², K. Taniguchi², and I. Ohdomari¹ ¹Waseda Univ. and ²Osaka University, Japan
14:50 2-6	Monte Carlo Investigation of Potential Fluctuation in 3D Device Structure Y. Ohkura C. Suzuki, N. Mise, T. Matsuki, T. Eimori, and M. Nakamura Semicon. Leading Edge Technologies, Inc., Japan

15:10 Break

Session 3: Memory (CONVENTION HALL [HAKONE higashi+naka])
Chairpersons: Y. Ohkura, Selete
　　　　　　　　　　 Y.-K. Park, Samsung

15:30 3-1	Full 3D String-Level Simulation of NAND Flash Device U-H. Kwon, M. Nakamura, Y. Ohkura, H. Ishikawa, and Y. Ohji Semicon. Leading Edge Technologies, Inc., Japan
15:50 3-2	Evaluating the Effects of Physical Mechanisms on the Program, Erase and Retention in the Charge Trapping Memory Y.C. Song¹, X.Y. Liu¹, Z.Y. Wang¹, K. Zhao¹, G. Du¹, J.F. Kang¹, R.Q Han¹, Z.L. Xia², D. Kim², and K.-H. Lee² ¹Peking Univ., China and ²Samsung Electronics Co. Ltd, Koera
16:10 3-3	Transient Device Simulation of Trap-Assisted Leakage in Non-Volatile Memory Cell H. Watanabe Toshiba Corp., Japan
16:30 3-4	Modeling the V_TH Fluctuations in Nanoscale Floating Gate Memories A. Calderoni, P. Fantini, A. Ghetti, and A. Marmiroli Numonyx, Italy
16:50 3-5	Micro Magnetic Simulation of Write Error Probability in STT-MRAM K. Kawabata, M. Tanizawa, K. Ishikawa, and Y. Inoue Renesas Technol. Corp., Japan
17:10 3-6	Phase-Change Memory Simulations Using an Analytical Phase Space Model B. Schmithusen¹, P. Tikhomirov¹, and E. Lyumkis² ¹Synopsys Switzerland LLC, Switzerland and ²Synopsys Inc., USA

18:00 Reception (CONVENTION HALL [HAKONE nishi])

Wednesday, September 10

Session 4: Noise and Reliability (CONVENTION HALL [HAKONE naka] )
Chairpersons: T. Ezaki, Hiroshima Univ.
　　　　　　　　　　 C. Mouli, Micron Semiconductor

10:00 4-1	A Unified Approach for the Reliability Modeling of MOSFETs (Invited) C.-K. Baek¹, S. Choi¹, H.-H. Park¹, J.-M. Woo¹, S.-M. Hong², C.H. Park³, and Y.J. Park¹ ¹Seoul National Univ., Korea, ²Bundeswehr Univ., Germany, and ³Kwangwoon Univ., Korea
10:30 4-2	Modeling Bias Temperature Instability During Stress and Recovery T. Grasser¹, W. Goes¹, and B. Kaczer² ¹TU Wien, Austria and ²IMEC, Leuven, Belgium
10:50 4-3	Level Shifts and Gate Interfaces as Vital Ingredients in Modeling of Charge Trapping W. Goes, M. Karner, S. Tyaginov, P. Hehenberger, and T. Grasser TU Wien, Austria
11:10 4-4	Investigation of Noise in Silicon Nanowire Transistors through Quantum Simulations H.-H. Park¹, S. Jin², S.Y. Park¹, H.S. Min¹ and, Y.J. Park¹ ¹Seoul National Univ., Korea and ²Synopsys Inc., USA
11:30 4-5	Statistical Analysis of Random Telegraph Noise in CMOS Image Sensors J.-M. Woo¹, H.-H. Park¹, S.-M. Hong², C.H. Park³, H.S. Min¹, and Y.J. Park¹ ¹Seoul National Univ., Korea, ²Bundeswehr Univ., Germany and ³Kwangwoon Univ., Korea

Session 5: New Function Device (CONVENTION HALL [HAKONE higashi])
Chairperson: K. Fukuda, Oki Electric Ind. Co., Ltd.
　　　　　　　　　　N. Nakano, Keio Univ.

10:30 5-1	Numerical Study of Carbon Nanotube Infra-Red Photo-Detectors M. Pourfath and H. Kosina TU Wien, Austria
10:50 5-2	Self-Consistent Simulation of Schottky Barrier SpinFET J. Liu, G. Du, J. Cao, Y. Wang, J.F. Kang, R. Han, and X. Liu Peking Univ., China
11:10 5-3	Interpretation of Laser Absorption Measurements on 4H-SiC Bipolar Diodes by Numerical Simulation D. Werber and G. Wachutka Munich Univ. of Technol., Germany
11:30 5-4	Numerical Modeling of a Deoxyribonucleic Acid Microassay: Carbon Nanotube Thin Film Transistor Sensor A. Akturk¹, N. Goldsman¹, H. Pandana¹, R. Gomez¹, and J. Khan² ¹Univ. of Maryland and ²National Institutes of Health, USA

11:50 Lunch

Session 6: Performance Booster (CONVENTION HALL [HAKONE naka])
Chairpersons: M. Kimura, Sony
　 T. Krishnamohan, Stanford Univ. and Intel Corp.

13:30 6-1	Band-engineering of Novel Channel Materials for High Performance Nanoscale MOSFETs (Invited) T. Krishnamohan Stanford Univ. and Intel Corp., USA
14:00 6-2	Performance Evaluation of Uniaxial- and Biaxial-Strained In_(x)Ga_(1-x)As NMOS DGFETs D. Kim¹, T. Krishnamohan^1,2, and K.C. Saraswat¹ ¹Stanford Univ. and ²Intel Corp., USA
14:20 6-3	Transport Masses in Strained Silicon MOSFETs with Different Channel Orientations D. Rideau, M. Feraille, M. Michaillat, C. Tavernier, and H. Jaouen STMicroelectronics, France

14:40 Break

15:00 6-4	Study of Stress Effect on Replacement Gate Technology with Compressive Stress Liner and eSiGe for pFETs S. Yamakawa¹, S. Mayuzumi¹, J. Wang¹, Y. Tateshita¹, H. Wakabayashi¹, T. Ohno¹, H. Ansai¹, D.Kosemura², M. Takei², and A. Ogura² ¹SONY Corp. and ²Meiji Univ., Japan
15:20 6-5	Source/Drain Engineering for High-Performance Deep Sub-100nm Ge-pMOSFETs Using Full-Band Monte Carlo Simulation H. Takeda¹, T. Ikezawa², M. Kawada², and M. Hane¹ ¹NEC Electronics Corp. and ²NEC Informatec Systems, Ltd., Japan
15:40 6-6	Progress in Modeling of SMT “Stress Memorization Technique” and Prediction of Stress Enhancement by a Novel PMOS SMT Process X. Wang and J. Wu Texas Instruments Inc., USA
16:00 6-7	Impact of Inhomogeneous Strain on the Valence Band Structures of Ge-Si Core-Shell Nanowires Y. He, C. Fan, Y.N. Zhao, G. Du, X.Y. Liu, and R. Han Peking Univ., China

16:30-18:30 Poster Session (CONVENTION HALL [HAKONE higashi])

P-1	Is Dual Gate Device Structure Better From Thermal Perspective? S.M. Goodnick¹, D. Vasileska¹, and K. Raleva² ¹Arizona State Univ., USA and ²Univ. Cyril and Metodi, Republic of Macedonia
P-2	Consistent Higher-Order Transport Models for SOI MOSFETs M. Vasicek, J. Cervenka, M. Karner, and T. Grasser TU Wien, Austria
P-3	An Analytical 2D Current Model of Double-Gate Schottky-Barrier MOSFETs Y.N. Zhao, G. Du, J.F. Kang, X.Y. Liu, and R. Han Peking Univ., China
P-4	Analytical Model for Point and Line Tunneling in a Tunnel Field-Effect Transistor W.G. Vandenberghe^1,2, A.S. Verhulst^1,2, G. Groeseneken^1,2, B. Soree², and W. Magnus^2,3 ¹K.U.Leuven, ²IMEC, and ³Univ. Antwerpen, Belgium
P-5	Ultra High Performance Insulator Channel Transistor D. Zhang¹, M. Ferrier¹, P. Griffin¹, T. Skotnicki², and Y. Nishi¹ ¹Stanford Univ., USA and ²ST Microelectronics, France
P-6	Mobility Enhancement in Thin Silicon Films: Strain and Thickness Dependences of Effective Mass and Non-Parabolicity Parameter V. Sverdlov, T. Windbacger, and S. Selberherr TU Wien, Austria
P-7	Strain Effects on Ballistic Current in Ultrathin DG SOI MOSFETs H. Minari and N. Mori Osaka Univ., Japan
P-8	3D Monte Carlo Simulation of Tri-Gate MOSFETs Using Tetrahedral Finite Elements M. Aldegunde¹, A.J. García-Loureiro¹, A. Martinez², and K. Kalna² ¹Univ. de Santiago de Compostela, Spain and ²Univ. of Glasgow, UK
P-9	A Complete Charge Based Compact Model for Silicon Nanowire FETs including Doping and Advanced Physical Effects F. Liu^1,2, J. He^1,2, L. Zhang², J. Zhang², J. Hu², X. Zhang^1,2, and M. Chan³ ¹Peking Univ. Shenzhen Graduate School, ²Peking Univ., and ³The Hong Kong Univ. of Science & Technol., China
P-10	Simulation of Self Gating Effect of a Liquid Gate Carbon Nanotube Field Effect Transistor G.S. Choe, D.W. Kim, J.-H. Cheon, S.M. Seo, and Y.J. Park Seoul National Univ., Korea
P-11	Comparative Simulation Study of GNR-FETs Using EHT- and TB-Based NEGF M. Zhang, Q. Ran, X. Guan, J. Zhang, Y. Wang, and Z. Yu Tsinghua Univ., China
P-12	Simulation of Single and Multi-Layer Graphene Field-Effect Devices M.G. Ancona Naval Res. Lab, USA
P-13	Unusually Strong Temperature Dependence of Graphene Electron Mobility A. Akturk and N. Goldsman Univ. of Maryland, USA
P-14	Electronic and Transport Properties of GaN/AlGaN Quantum Dot-Based p-i-n Diodes F. Sacconi, G. Romano, G. Penazzi, M. Povolotskyi, M. Auf der Maur, A. Pecchia, and A. Di Carlo Univ. of Rome ”Tor Vergata”, Italy
P-15	Effects of Quantum Confinement on Interface Trap Occupation in 4H-SiC MOSFETs S. Potbhare¹, A. Akturk¹, N. Goldsman¹, and A. Lelis² ¹Univ. of Maryland and ²S. Army Res. Lab., USA
P-16	Analysis and Modeling of Capacitance-Voltage Characteristics of Poly-Si TFTs Using Device Simulation. H. Tsuji, T. Kuzuoka, Y. Kamakura, and K. Taniguchi Osaka Univ., Japan
P-17	Organic Thin-Film Transistors Modeling; Simulation and Design of a Fully Organic AMOLED O. Yaghmazadeh¹, Y. Bonnassieux¹, G. Horowitz², B. Geffroy³, D. Tondelier³, and A. Saboundji¹ ¹Ecole Polytechnique, ²Université Paris-Diderot, and ³Ecole Polytechnique, France
P-18	Simulation of Field-Effect Biosensors (BioFETs) T. Windbacher¹, V. Sverdlov¹, S. Selberherr¹ , C. Heitzinger², N. Mauser², and C. Ringhofer³ ¹TU Wien and ²Univ. of Vienna, Austria and ³Arizona State Univ., USA
P-19	Effect of Contacts on the Terahertz Plasma Resonances in Two-Dimensional Electron Systems A. Satou¹, V. Ryzhii¹, N. Vagidov², V. Mitin², and T. Otsuji³ ¹Univ. of Aizu, Japan, ²Univ. at Buffalo, USA, and ³Tohoku Univ., Japan
P-20	Numerical Modeling and Design of Single Photon Counter 4H-SiC Avalanche Photodiodes A. Akturk^1,2, N. Goldsman^1,2, S. Aslam³, J. Sigwarth³, and F. Herrero³ ¹Univ. of Maryland and ²CoolCAD Electronics, and ³NASA Goddard Space Flight Center, USA
P-21	Emission Efficiency Dependence on the Tilted Angle of Nanogaps in Surface Conduction Electron-Emitter Y. Li¹, Y.-T. Kuo¹, H.-W. Cheng¹, T.-C. Yeh¹, H.-Y. Lo¹, M.-T. Chiang², and C.-N. Mo² ¹National Chiao Tung Univ. and ²Chunghwa Picture Tubes, Ltd., Taiwan
P-22	Reduction of Discrete-Dopant-Induced High-Frequency Characteristic Fluctuations in Nanoscale CMOS Circuit Y. Li, C.-H. Hwang, T.-C. Yeh, H.-M. Huang, T.-Y. Li, and H.-W. Cheng National Chiao Tung Univ., Taiwan
P-23	Effect of Random Impurities on Transport Characteristics of Nano-Scale MOSFET G. Mil’nikov¹, N. Mori¹, Y. Kamakura¹, and T. Ezaki² ¹Osaka Univ. and ²Hiroshima Univ., Japan
P-24	Effects of Wavefunction Modulation on Electron Transport in Ultrathin-Body DG MOSFETs N. Mori and H. Minari Osaka Univ., Japan
P-25	Analysis of Direct Tunneling Current from Quasi-Bound States in n-MOSFET Based on Non-Equilibrium Green's Function S. Muraoka, S. Souma, and M. Ogawa Kobe Univ., Japan
P-26	Study on the Optimized Design of Nanowire Tunneling Transistors including Quantum Effects A. Heigl and G. Wachutka TU München, Germany
P-27	Band Calculation for the Hexagonal and FCC Chalcogenide Ge₂Sb₂Te₅ E. Piccinini^1,3, T. Tsafack¹, F. Buscemi^1,3, R. Brunetti^2,3, M. Rudan¹, and C. Jacoboni^2,3 ¹Univ. of Bologna, ²Univ. of Modena and Reggio Emilia, and ³CNR-INFM National Center on nanoStructures and bioSystems at Surfaces (S³), Italy
P-28	First-Principles Calculations for Effects of Fluorine Impurity in GaN J. Lu, M. Gao, J. Zhang, Y. Wang, and Z. Yu Tsinghua Univ., China
P-29	Analysis of Electromigration in Redundant Vias R.L. de Orio¹, H. Ceric¹, S. Carniello², and S. Selberherr¹ ¹TU Wien and ²Schloss Premstätten, Austria
P-30	Analysis of Microstructure Impact on Electromigration H. Ceric, R.L. de Orio, J. Cervenka, and S. Selberherr TU Wien, Austria
P-31	3-D Stress Simulation using Simple Quasi-Models of Gate Oxidation and Silicidation M. Fujinaga¹, T. Yamauchi¹, S. Kamohara², and A. Nishida² ¹TCAD International Inc. and ²Semicon. Leading Edge Technol. Corp.(Selete-MIRAI), Japan
P-32	Ion Implantation Model for Channeling through Multi-Layers T. Yamanaka¹, M. Mochizuki², H. Hayashi², K. Fukuda², K. Sasaki³, Y. Doi³, H.D. Nguyen⁴, and K.Nishi¹ ¹Kinki Univ. Tech. Col., ²Oki Electric Ind. Co. Ltd., ³Miyazaki Oki Electric Co. Ltd., and ⁴Kinki Univ.,Japan
P-33	Analytical Model and Monte Carlo Simulations for Phosphorus Implantation in Germanium including Ion Channeling G. Hellings^1,2, G. Eneman^1,2,3, M. Meuris², and K. De Meyer ^1,2 ¹Interuniversity Microelectronics Center (IMEC) and ²Univ. of Leuven, Belgiumm
P-34	A Highly Effective and Efficient Cost-Function-Reduction Method for Inverse Lithography Technique J. Zhang¹, M.-C. Tsai², W. Xiong¹, Y. Wang¹, and Z. Yu¹ ¹Tsinghua Univ., China and ²Synopsys Inc., USA
P-35	Convergence Properties of Density Gradient Quantum Corrections in 3D Ensemble Monte Carlo Simulations C. Riddet and A. Asenov Univ. of Glasgow, UK
P-36	A Robust Parallel Delaunay Mesh Generation Approach Suitable for Three-Dimensional TCAD F. Stimpfl, R. Heinzl, P. Schwaha, and S. Selberherr TU Wien, Austria
P-37	Operational PRAM Analysis with PVT Variations Using Process-Aware Compact Model Y.T. Kim, Y.G. Kim. G.Y. Yang, K.H. Lee, H. Horii, H.G. An, J.H. Kong, K.J. Lee, M.H. Park, Y.K. Park, and M.H. Yoo Samsung Electronics Co., Ltd., Korea
P-38	A Surface Potential Model for Bulk MOSFET which Accurately Reflects Channel Doping Profile Expelling Fitting Parameters H. Sakamoto, K. Watanabe, H. Arimoto, M. Tanizawa, and S. Kumashiro MIRAI-Selete, Japan

Thursday, September 11

Session 7: Transport and Mobility (CONVENTION HALL [HAKONE naka])
Chairperson: Y. Kamakura, Osaka Univ.
　　　　　　　　　　M.D. Profirescu, Univ. Politehnica of Bucharest.

9:20 7-1	Wigner Monte Carlo Approach to Quantum Transport in Nanodevices (Invited) P. Dollfus, D. Querlioz, J. Saint-Martin, V.-N. Do, and A. Bournel Univ. Paris-Sud, France
9:50 7-2	Three-Dimensional Quantum Transport Simulation of Si-Nanowire Transistors Based on Wigner Function Model Y. Yamada and H. Tsuchiya Kobe Univ., Japan
10:10 7-3	Phonon Transport in Electronic Devices: From Diffusive to Ballistic Regime B. Thouy, J.-P. Mazellier, J.-C. Barbe, and G. Le Carval CEA-LETI MINATEC, France
10:30 7-4	A Theoretical Study of Electron Mobility Reduction due to Acoustic Phonon Modulation in a Free-Standing Semiconductor Nanowire J. Hattori^1,3, S. Uno^1,3, N. Mori², and K. Nakazato^1,3 ¹Nagoya Univ. and ²Osaka Univ. and ³SORST JST, Japan

10:50 Break

11:10 7-5	A Deterministic Boltzmann Equation Solver for Two-Dimensional Semiconductor Devices S.-M. Hong¹, C. Jungemann¹, and M. Bollhoefer² ¹Bundeswehr Univ. and ²TU Braunschweig, Germany
11:30 7-6	Coupling the Monte-Carlo Method with Semi-Analytical Solutions of the Boltzmann Transport Equation S.C. Brugger¹, V. Peikert², and A. Schenk² ¹Numerical Solutions GmbH and ²ETH Zurich, Switzerland
11:50 7-7	2D Simulation of Gate Currents in MOSFETs: Comparison between S-Device and the Quantum Mechanical Simulator GreenSolver A. Schenk¹ and M. Luisier² ¹ETH Zurich, Switzerland and ²Purdue Univ., USA
12:10 7-8	Modulated Exchange and Gate Oxide Thickness Effects on Surface Roughness Limited Mobility S. Wakahara Renesas Technol. Corp., Japan

Session 8: Device Design (CONVENTION HALL [HAKONE higashi])
Chairpersons: S. Dunham, Univ. of Washington.
　　　　　　　　　　 M. Hane, NEC Electronics Corp

9:50 8-1	Device Scaling of High Performance MOSFET with Metal Gate High-K at 32nm Technology Node and Beyond X. Wang¹, G. Shahidi², P. Oldiges¹, and M. Khare¹ ¹IBM Semicon. Research and Development Center and ²IBM T.J. Watson Research Center, USA
10:10 8-2	Air-Spacer Self-Aligned Contact MOSFET for Future Dense Memories J. Park and C. Hu Univ. of California, USA
10:30 8-3	Advanced Annealing Strategies for the 32 nm node C. Kampen¹, A. Martinez-Limia¹, P. Pichler^1,2, A. Burenkov¹, J. Lorenz¹, and H. Ryssel^1,2 ¹Fraunhofer Inst. of Integrated Systems and Device Technol. (IISB) and ²Univ. of Erlangen-Nuremberg, Germany

10:50 Break

11:10 8-4	Monte Carlo Simulation of Cu-Resistivity Z.Y. Wang, G. Du, J.F. Kang, X.Y. Liu, and R. Han Peking Univ., China
11:30 8-5	Three-Dimensional Topography Simulation Using Advanced Level Set and Ray Tracing Methods O. Ertl and S. Selberherr TU Wien, Austria
11:50 8-6	Atomistic Approach for Boron Transient Enhanced Diffusion and Clustering A. Mauri¹, L. Laurin², F. Montalenti², and A. Benvenuti¹¹STMicroelectronics and ²Univ. of Milano, Italy
12:10 8-7	Atomistic Modeling of Dopant Diffusion and Segregation in Strained SiGeC S.T. Dunham, H.-W. Guo, C. Ahn, and J. Song Univ. of Washington, USA

12:30 Lunch

Session 9: Quantum Transport (CONVENTION HALL [HAKONE naka])

Chairpersons: N. Mori, Osaka Univ
　　　　　　　　　　　G. Wachutka, Technische Univ. Muenchen

14:00 9-1	2D/3D NEGF Modeling of the Impact of Random Dopants/Dopant Aggregation in SiliconNano-Transistors (Invited) J. Barker Univ. Glasgow, UK
14:30 9-2	Simulation of Impurities with Attractive Potential in Fully 3-D Real-Space Non-Equilibrium Green's Function Quantum Transport Simulations A. Martinez¹, J. R. Barker¹, A. R. Brown¹, N. Seoane^1,2, and A. Asenov¹ ¹Univ. of Glasgow, UK and ²Univ. Santiago de Compostela, Spain
14:50 9-3	Coupling of Non-Equilibrium Green’s Function and Wigner Function Approaches O. Baumgartner, P. Schwaha, M. Karner, M. Nedjalkov, and S. Selberherr TU Wien, Austria

15:10 Break

15:30 9-4	A Self-Consistent Calculation of Band Structure in Silicon Nanowires Using a Tight-Binding Model E. Sarrazin^1,2, S. Barraud¹, F. Triozon¹, and A. Bournel² ¹CEA/LETI-Minatec and ²Univ. Paris-Sud, France
15:50 9-5	Modeling of High-k-Metal-Gate-Stacks Using the Non-Equilibrium Green's Function Formalism O. Baumgartner, M. Karner, and H. Kosina TU Wien, Austria
16:10 9-6	Effect of Interface Characteristics of W/HfO_2±x on Electronic Reliability : Quantum Chemical Molecular Dynamics Study K. Suzuki, T. Inoue, and H. Miura Tohoku Univ., Japan
16:30 9-7	Physics of Tunneling from a Macroscopic Perspective M.G. Ancona¹ and A. Svizhenko² ¹Naval Res. Lab and ²Silvaco Data Systems, USA

Session 10: Circuit Simulation (CONVENTION HALL [HAKONE higashi])
Chairpersos: K. Ishikawa, Renesas Technology Corp.
　　　　　　　　　　　V. Axelrad, Sequoia Design System.

14:30 10-1	Synthetic Soft Error Rate Simulation Considering Neutron-induced Single Event Transient from Transistor to LSI-chip level M. Hane, H. Nakamura, K. Tanaka, K. Watanabe, Y. Tosaka, K. Ishikawa, and S. Kumashiro MIRAI-SELETE, Japan
14:50 10-2	Analysis of Temperature and Process Variation Effects of Photo Sensor Circuit Using Device/Circuit Mixed-Mode Simulations M. Mochizuki, H. Hayashi, T. Chiba, and K. Fukuda Oki Electric Ind. Co., Ltd., Japan

15:10 Break

15:30 10-3	A Surface Potential Based Poly-Si TFT Model for Circuit Simulation S. Miyano¹, Y. Shimizu¹, T. Murakami², and M. Miura-Mattausch² ¹Advanced LCD Technologies Development Center Co. Ltd. and ²Hiroshima Univ., Japan
15:50 10-4	A New Unified Compact Model for Quasi-Ballistic Transport: Application to the Analysis of Circuit Performances of a Double-Gate Architecture S. Martinie^1,2, D. Munteanu², G. Le Carval¹, and J. L. Autran^2,3 ¹CEA-LETI MINATEC and ²IM2NP-CNRS and ³Univ. Insti. of France (IUF), France
16:10 10-5	Non-Quasi-Static Carrier Dynamics of MOSFETs under Low-Voltage Operation M. Miyake¹, D. Hori¹, N. Sadachika¹, U. Feldmann¹, M. Miura-Mattausch¹, H.J. Mattausch¹, T. Iizuka², K. Matsuzawa², Y. Sahara², T. Hoshida², and T. Tsukada² ¹Hiroshima Univ. and ²Semicon. Technol. Academic Res. Center, Japan