Workshop on Gate Stack and Contact Engineering for sub-30nm FETs

September 5, 2006 • Monterey Plaza Hotel • Monterey • CA • USA

Organizers: Robert Dutton, Paul McIntyre, Yoshio Nishi, and Krishna Saraswat, Stanford University

This workshop is targeted at the discussion of critical issues facing scaled MOS technology with emphasis on the gate stack and contact technologies. There are many challenges both in terms of technology and device design that need to be considered. It is now generally accepted that alternative materials are needed to maintain good electrostatics and to reduce parasitic effects. This workshop will explore these issues based on experimental and modeling work of leading experts in the field.

Tuesday, September 5, 2006
Monterey Plaza Hotel • Monterey • CA • USA

Session I: Scaling Challenges (Chair: R. Dutton)

8:30 D. Antoniadis (MIT)--Transistor Performance Scaling

9:00 K. Saraswat (Stanford)--Performance Limitations of Si Bulk CMOS and Alternatives for Nanoelectonics

9:30 J. Welser (IBM)--Scaling Issues Involving Strained Materials

10:00 H.-S. P. Wong (Stanford)--Device Opportunities of Nanotechnology

Break

Session II: Metal Gate and High K Dielectrics I (Chair: P. McIntyre)

11:00 L. Colombo (TI)--Progress in Metal Gate/High K Process Integration Challenges

11:30 G. Pourtois (IMEC)--Collaborative Development Efforts

12:00 V. Misra (NC State)--Ternary Alloy Systems for Metal Gate on High K

Lunch

Session III: Metal Gate and High K Dielectrics II (Chair: Y. Nishi)

1:30 B. H. Lee (Sematech)--Strategy to Scale Gate Stack Technology for sub-30nm MOSFETs

2:00 G. Kittl (IMEC)--FUSI Metal Gate Integration Issues

2:30 H. Jaouen, T. Skotnicki (ST Micro)--NiSi TOSI for Metal Gate

3:00 KJ Cho (Stanford)-- Metal Gate Work Function Engineering, Experimental and Theoretical Study

Break

Session IV: Contact Technology (Chair: K. Saraswat)

3:45 D. Connelly (Acorn)--Zero-Barrier Metal Source/Drain MOSFETs

4:15 S. Takagi (U. Tokyo)--Metal Source/Drain Ge MOSFET Technologies

4:45 T.-J. King (UCB)--Metal Semiconductor Contact Work Function Engineering

5:15 M. Ozturk (NC State)--Low Contact Resistance Source/drain MOSFET Technology

To register for the workshop, please go to SISPAD '06 registration site. There is a space that will allow the user to register for the workshop.
sispad06@gloworm.stanford.edu

Back to SISPAD 06 homepage

Tuesday, September 5, 2006 Monterey Plaza Hotel • Monterey • CA • USA
	Session I: Scaling Challenges (Chair: R. Dutton)
8:30	D. Antoniadis (MIT)--Transistor Performance Scaling
9:00	K. Saraswat (Stanford)--Performance Limitations of Si Bulk CMOS and Alternatives for Nanoelectonics
9:30	J. Welser (IBM)--Scaling Issues Involving Strained Materials
10:00	H.-S. P. Wong (Stanford)--Device Opportunities of Nanotechnology
	Break
	Session II: Metal Gate and High K Dielectrics I (Chair: P. McIntyre)
11:00	L. Colombo (TI)--Progress in Metal Gate/High K Process Integration Challenges
11:30	G. Pourtois (IMEC)--Collaborative Development Efforts
12:00	V. Misra (NC State)--Ternary Alloy Systems for Metal Gate on High K
	Lunch
	Session III: Metal Gate and High K Dielectrics II (Chair: Y. Nishi)
1:30	B. H. Lee (Sematech)--Strategy to Scale Gate Stack Technology for sub-30nm MOSFETs
2:00	G. Kittl (IMEC)--FUSI Metal Gate Integration Issues
2:30	H. Jaouen, T. Skotnicki (ST Micro)--NiSi TOSI for Metal Gate
3:00	KJ Cho (Stanford)-- Metal Gate Work Function Engineering, Experimental and Theoretical Study
	Break
	Session IV: Contact Technology (Chair: K. Saraswat)
3:45	D. Connelly (Acorn)--Zero-Barrier Metal Source/Drain MOSFETs
4:15	S. Takagi (U. Tokyo)--Metal Source/Drain Ge MOSFET Technologies
4:45	T.-J. King (UCB)--Metal Semiconductor Contact Work Function Engineering
5:15	M. Ozturk (NC State)--Low Contact Resistance Source/drain MOSFET Technology