Technical Program:
September 6, 2006
September 7, 2006,
Poster Session
Session 9 - Scaling
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| 9:15 - 9:40 9-1 |
"Simulation Study on Channel Length Scaling of High
Performance Partially Depleted Metal Gate and Poly Gate
SOI MOSFETs" X. Wang, A. Bryant, P. Oldiges, S. Narasimha, R. Dennard, W. Haensch, IBM Semiconductor Research and Development Center, Hopewell Junction, NY |
| 9:40 - 10:05 9-2 |
"Scaling Limit of CMOS Supply Voltage from Noise
Margin Considerations" M. Liu, M. Cai, Y. Taur, University of California, San Diego, San Diego, CA |
| Break (15 minutes) | |
| 10:20 - 10:45 9-3 |
"Power/Performance Based Scalability Comparisons between Conventional
and Novel Transistors Down to 32nm Technology Node" P. Kapur, R.S. Shenoy, K.C. Saraswat, Stanford University, Stanford, CA |
| 10:45 - 11:10 9-4 |
"Effect of Body Doping on the Scaling of Ultrathin
SOI MOSFETs" W-Y. Lu, Y. Taur, University of California, San Diego, La Jolla, CA |
| 11:10 - 11:35 9-5 |
"Simulation Study of a Metal/High-k Gate Stack for Low-
Power Applications" A. Kumar, P.M. Solomon, IBM Semiconductor Research and Development Center, Yorktown Heights, NY |
| 11:35 - 12:00 9-6 |
"Scaling Limits of Capacitorless Double Gate DRAM Cell" N. Butt, M. Alam, Purdue University, West Lafayette, IN |
Session 10 - Gate Stack, Interface, and Leakage | |
8:30 - 9:15 I-6 |
Invited Speaker "Theory of Fermi Level Pinning of High-k Dielectrics" Kenji Shiraishi, Hideki Takeuchi*, University of Tsukuba, Ibaraki, Japan, *ATDF Inc., Austin, TX |
9:15 - 9:40 10-1 |
"Strain Effects on Quasi-Bound State Tunneling in Advanced SOI CMOS Technologies" M. Karner, E. Ungersboeck, A. Gehring*, S. Holzer, H. Kosina, S. Selberherr, TU Vienna, Vienna, Austria, *AMD Saxony, Dresden, Germany |
| 9:40 - 10:05 10-2 |
"A Madelung Fluid Based Density Gradient Model for
Large Barrier Tunneling Calculations" V. Narayanan, E.C. Kan, Cornell University, Ithaca, NY |
| Break (15 minutes) | |
| 10:20 - 10:45 10-3 |
"Monte Carlo Simulation of Charge Carrier Injection in
Twin Flash Memory Devices during Program and Erase" R. Hagenbeck, S. Decker*, P. Haibach, C. Jungemann**, T. Mikolajick***, G. Tempel****, M. Isler***, B. Meinerzhagen*****, Qimonda, Munich, Germany, *Infineon Technologies AG, Munich, Germany, **Bundeswehr University Munich, Neubiberg, Germany, ***Qimonda, Dresden, Germany, ****Infineon Technologies, Dresden, Germany, *****Technical University Braunschweig, Braunschweig, Germany |
| 10:45 - 11:10 10-4 |
"A New Statistical Model for the SILC Distribution of Flash
Memory and the Effect of Spatial Trap Distribution" B.S. Shim, S. Jin, Y.J. Park, H.S. Min, Seoul National University, Seoul, Korea |
| 11:10 - 11:35 10-5 |
"TCAD Modeling of Negative Bias Temperature Instability" T. Grasser, R. Entner, O. Triebl, H. Enichlmair*, R. Minixhofer*, TU Vienna, Vienna, Austria, *Austriamicrosystems, Unterpremstaetten, Austria |
| 11:35 - 12:00 10-6 |
"Modeling of the Leakage Current Distribution of 16M
Stacked Single Crystal (SC)- like SOI pMOS Transistors
using Green's Function Method" B. Hwang, B.S. Shim, S. Jin, I-Y. Chung*, S-M. Jung,** K.Kim**, Y.J. Park, H.S. Min, Seoul National University, Seoul, Korea, *Gyeongsang National University, Korea, **Samsung Electronics, Korea |
Session 11 - Interconnect and Backend | |
| 1:30 - 1:55 11-1 |
"A 3-D Time-Dependent Green's Function Approach to
Modeling Electromagnetic Noise in On-Chip Interconnect
Networks" Z. Dilli, N. Goldsman, A. Akturk, G. Metze*, University of Maryland, College Park, MD *Laboratory for Physical Sciences, College Park, MD |
| 1:55 -2:20 11-2 |
"Mesoscopic Resist Processing Simulation in Optical Lithography" T. Schnattinger, E. Bar, A. Erdmann Fraunhofer Institute of Integrated Systems and Device Technology, Erlangen, Germany |
| 2:20 - 2:45 11-3 |
"Grain Based Modeling of Stress Induced Copper
Migration for 3D-IC Interwafer Vias" D. N. Bentz, M. O. Bloomfield, H. Huang, J-Q. Lu, R. J. Gutmann, T. S. Cale, Rensselaer Polytechnic Institute, Troy, NY |
| 2:45 - 3:10 11-4 |
"Contact Structure Formation in Carbon Nanotube
Electronic Devices and its Effect on Electron Transport" K. Ravichandran, W. Luo, W. Windl, L. R. C. Fonseca*, The Ohio State University, Columbus, OH, *Universidade Estadual de Campinas, Campinas, Brazil |
Session 12 - Device Physics: Advanced Physical Models | |
| 1:30 - 1:55 12-1 |
"Development of a Full 3D NEGF Nano-CMOS Simulator" A. Martinez, J. R. Barker, A. Asenov, M. Bescond*, A. Svizhenko**, A. Anantram***, University of Glasgow, Scotland, UK, *IMEP-ENSPG, Grenoble, France, **Stanford University, Stanford, CA, ***Univeristy of Waterloo, Canada |
| 1:55 - 2:20 12-2 |
"Wigner Monte Carlo Simulation: Particle Annihilation
and Device Applications" H. Kosina, V. Sverdlov, T. Grasser, TU Vienna, Vienna, Austria |
| 2:20 - 2:45 12-3 |
"A Full-Band Spherical Harmonics Expansion of the
Valence Bands up to High Energies" A.T. Pham, C. Jungemann*, B. Meinerzhagen, TU Braunschweig, Braunschweig, Germany, *Universitaet der Bundeswehr Munchen, Germany |
| 2:45 - 3:10 12-4 |
"First Self-Consistent Full-Band 2D Monte Carlo 2D
Poisson Device Solver for Modeling SiGe Heterojunction
p-Channel Devices" S. Krishnan, D. Vasileska*, Intel Corporation, Chandler, AZ, *Arizona State University, Tempe, AZ, |
Session 13 - Applications: Process | |
| 3:30 - 3:55 13-1 |
"Multiple Type Grid Approach for 3D Process Simulation" D. Kimpton, M. Baida, V. Zhuk, M. Temkin, I. Chakarov, Silvaco International, Santa Clara, CA |
| 3:55 - 4:20 13-2 |
"3-D Process Simulation of CMOS Inverter Based on Selete
65nm Full Process" M. Fujinaga, S. Itoh, M. Mochiduki, T. Uchida, H. Ishikawa, M. Takenaka, C. J. Park, S. Asada, T. Shinzawa, J. Namekata, S. Wakahara, T. Wada, Selete, Ibaraki, Japan |
| 4:20 - 4:45 13-3 |
"A Full 3D TCAD Simulation Study of Line-Width
Roughness Effects in 65nm Technology" L. Sponton, L. Bomholt*, D. Pramanik**, W. Fichtner*, ETH-Zurich, Switzerland, *Synopsys Switzerland LLC, Zurich, Switzerland, **Synopsys, Inc., Mountain View, CA |
| 4:45 - 5:10 13-4 |
"Monte Carlo Simulation of Boron Implantation into (100)
Germanium" R. Wittmann, A. Hoessinger, J. Cevenka, S. Uppal*, S. Selberherr, TU Vienna, Wien, Austria, *University of Newcastle upon Tyne, Newcastle, United Kingdom |
Session 14 - Novel Devices | |
| 3:30 - 3:55 14-1 |
"Novel Asymmetric Raised Source/Drain Extension MOSFET" T. Imoto, Y. Tateshita, T. Kobayashi, Sony Corporation, Atsugi-shi, Kanagawa, Japan |
| 3:55 - 4:20 14-2 |
"Band to Band Tunneling Limited Off State Current in
Ultra-thin Body Double Gate FETs with High Mobility
Materials: III-V, Ge and Strained Si/Ge" D. Kim, T. Krishnamohan, Y. Nishi, K.C. Saraswat, Stanford University, Stanford, CA |
| 4:20 - 4:45 14-3 |
"Analysis of Electronic Threshold of PRAM Cell Operation" Y-T. Kim, K-H. Lee, Y-K. Park, J-T. Kong, Samsung Electronics Co. Ltd., Gyeonggi-Do, Korea |
| 4:45 - 5:10 14-4 |
"Design Optimization of Large Area Si/SiGe
Thermoelectric Generators" M. Wagner, G. Span*, S. Holzer, O. Triebl, T. Grasser, TU Vienna, Wien, Austria, *SAM-band Mayrhofer KEG, Wattens, Austria |