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Thursday,
September 2, 2004 |
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Session 5: Device Analysis
Location: Conference
Room London
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| 14:00 |
Simulation Study of Simple CMOS-Compatible
Thin-SOI Vertical Bipolar Transistors on Thin BOX with an Inversion
Collector
Ouyang, Q., Ning, T. H.
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IBM
Semiconductor Research and Development Center (SRDC)
IBM Research Division, T. J. Watson Research Center, Yorktown Heights,
NY 10598 |
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14:20
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Current
collapse associated with surface states in GaN-based HEMT's.
Theoretical/experimental investigations
Sleiman1,
A., Di Carlo1, A., Verzellesi2, G., Meneghesso3,
G., Zanoni3, E.
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1 Dept. of Electronic
Engineering, University of Rome “Tor Vergata”, Italy
2
Dipartimento di Ingegneria dell’Informazione, Università di
Modena e Reggio Emilia, and
INFM, Italy
3
Dipartimento di Ingegneria dell’Informazione, Università di
Padova, and INFM, Italy
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14:40
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Implications
of Gate Misalignment for Ultra-narrow Multi-gate Devices
Krivokapic1,
Z., Moroz2, V.
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1 AMD,
Technology Research Group,M/S 143, One AMD Place, Sunnyvale, USA
2
Synopsis, Mountain View, USA
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| 15:00
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Coffee
Break
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15:30
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Source-Side
Injection Modeling by Means of the Spherical-Harmonics Expansion of the
BTE
Lorenzini,
M., Wellekens, D., Haspeslagh, L., Van Houdt, J.
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IMEC—Interuniversity
Microelectronics Center, Belgium |
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15:50
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Investigation
of a novel tunneling transistor by MEDICI simulation
Wang,
P.-F., Nirschl, T., Schmitt-Landsiedel, D., Hansch, W.
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Institute
for Technical Electronics, Technical University Munich, Germany |
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16:10
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Optimization
of BAW resonator performance using combined simulation techniques
Thalhammer,
R., Marksteiner, S.
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Infineon
Technologies, Germany |
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