Session 4: Stress Effects on Carrier
Transport
Location: Conference
Room New York
|
| 14:00 |
Theoretical Analysis of Stress and Surface
Orientation Effects on Inversion Carrier Mobility
Ezaki, T., Nakamura, H.,
Yamamoto, T., Takeuchi, K., Hane, M.
|
|
System
Devices Research Laboratories, NEC Corporation, Japan |
|
|
14:20
|
CMOS Circuit Performance Enhancement by
Surface Orientation Optimization
Chang, L., Ieong, M.,
Yang, M.
|
|
IBM
T.
J. Watson Research Center, USA |
|
|
14:40
|
Modeling of Stress Induced Layout Effect on
Electrical Characteristics of Advanced MOSFETs
Fujii, O., Yoshimura, H.,
Hasumi, R., Sanuki, T., Oyamatsu, H., Matsuoka, F., Noguchi, T.
|
|
Advanced
Logic Technology Department, System LSI Division I, Semiconductor
Company, Toshiba Corporation, Japan
|
|
|
| 15:00
|
Coffee Break
|
|
|
15:30
|
Hole Mobility Enhancement Modeling and
Scaling Study for High Performance Strained Ge Buried Channel PMOSFETs
Wang1, X.,
Shang2, H., Oldiges1, P., Rim2, K.,
Koester2, S., Ieong1, M.
|
|
IBM
Semiconductor Research and Development Center
1 Microelectronics Division, NY
2 Research Division, IBM T.J. Watson Research
Center |
|
|
15:50
|
Three-Dimensional Characterization and
Modelling of Stress Distribution in High-Density DRAM Memory Cells
Li1, J., Hull1,
R., Yang2, R., Hou2, V., Mouli2, C.
|
|
1
Department of Material Science and Engineering, University of Virginia,
Charlottesville
2 R&D, Micron Technology Inc, Boise
|
|
|
16:10
|
Strain Optimization to Reduce Gate Leakage
Current in MOS Transistors with Silicon Oxynitride Gate Dielectrics by
Use of First-Principles Calculations
Kanegae, Y., Moriya, H.,
Iwasaki, T
|
|
Mechanical
Engineering Research Laboratory, Hitachi, Ltd., Japan |
|
