Poster Session
Location: Forum
8
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| P1 |
2D
Quantum Mechanical (QM) Charge Model and Its Application to Ballistic
Transport of Sub-50nm Bulk Silicon MOSFETs
Zhang,
D., Zhu, G., Zhang, H., Tian, L., Zhiping, Y.
|
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Institute
of Microelectronics, Tsinghua University, Beijing, China |
|
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P2
|
Effective
Bohm Quantum Potential for device simulators based on drift-diffusion
and energy transport
Iannaccone,
G., Curatola, G., Fiori, G.
|
|
Dipartimento
di Ingegneria dell’Informazione, Università degli Studi di Pisa,
Pisa, Italy |
|
|
P3
|
Single
Ion and Multi Ion MOSFETs Simulation with Density Gradient Model
Toyabe,
T.
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|
Toyo
Univ. Bio-Nano Electronics Research Centre, Kawagoe, Japan |
|
|
P4
|
Modeling
and Simulation of Combined Thermionic Emission-Tunneling Current
through Interfacial Isolation Layer
Racko1,
J., Donoval1, D., Kudela1, P., Wachutka2,
G.
|
|
1
Slovak University of Technology, Bratislava, Slovakia
2 Munich University of Technology, Munich,
Germany |
|
|
P5
|
Experiments
on Minority Carrier Diffusion in Silicon: Contribution of Excitons
Mohrhof1,
J., Silber2, D.
|
|
1
REpower Systems AG, Rendsburg, Germany
2 Institute for Electrical Drives, Power
Electronics and Devices, University of Bremen, Germany |
|
|
P6
|
Accurate
Temperature Drift model of MOSFETs Mobility for Analog Circuits
Watanabe1,
K., Hamada1, T., Kotani1, K., Teramoto2,
A., Sugawa1, S., Ohmi1, T.
|
|
1
Graduate School of Engineering, Tohoku University
2 New Industry Creation Hatchery Center, Tohoku
University, Japan |
|
|
P7
|
Accurate
Modeling of Lattice Site-Dependent Ionization Level of Impurities in
α-SiC Devices
Ayalew1,
T., Grasser1, T., Kosina2, H., Selberherr2,
S.
|
|
1
Christian Doppler Laboratory for TCAD in Microelectronics at the
Institute for Microelectronics
2 Institute for Microelectronics, TU Vienna,
Austria |
|
|
P8
|
Strain
Scaling for Ultra Thin Silicon NMOS Devices
Krivokapic,
Z., Xiang, Q., Lin, M.-R.
|
|
AMD,
Technology Research Group,M/S 143, One AMD Place, Sunnyvale, USA
|
|
|
P9
|
CMOS
Scaling Analysis based on ITRS Roadmap by Three-dimensional Mixed-mode
Device Simulation
Tanabe,
R., Ashizawa, Y., Oka, H.
|
|
Fujitsu
Laboratories Ltd. Fuchigami 50, Akiruno, Tokyo, Japan |
|
|
P10
|
Comparison
of Nanoscale Metal-Oxide-Semiconductor Field Effect Transistors
Li1,2, Y., Lee1, J.-W., Chou3, H.-M.
|
|
1
Dept. of Computational Nanoelectronics, Nat’l Nano Device Lab.
2 Microelectronics & Information Systems
Research Center, Nat’l Chiao Tung Univ.
3 Dept. of Electrophysics, National Chiao Tung
Univ. Taiwan |
|
|
P11
|
Numerical
analysis for the structure dependence on the subthreshold slope of
Floating Channel type SGT(FC-SGT) Flash memory
Yamazaki,
H., Sakuraba, H., Masuoka, F.
|
|
Research
Institute of Electrical Communication, Tohoku University, Japan |
|
|
P12
|
A
Monte-Carlo Method for Distribution of Standby Currents and its
Application to DRAM Retention Time
Jin,
S., Yi, J.-H., Park, Y. J., Min H. S.
|
|
School
of Electrical Engineering and Nano-Systems Institute (NSI-NCRC), Seoul
National University, Kwanak-Gu, Seoul, Korea |
|
|
P13
|
Optimal
Contact Placement in Partially Depleted SOI with Application to Raised
Source-Drain Structures
Subba,
N., Luning, S., Riccobene, C., Feudel, T., Wei, A., Horstmann, M.
|
|
Advanced
Micro Devices, One AMD Place, Sunnyvale |
|
|
P14
|
Simulation
of Microstructure Formation during Thin Film Deposition
Bloomfield,
M. O., Cale, T. S.
|
|
Focus
Center—New York: Rensselaer, Rensselaer Polytechnic Institute, Troy, USA |
|
|
P15
|
Effect
of Stress on Pattern-Dependent Oxidation of Silicon Nanostructures
Uematsu1,
M., Kageshima1, H., Shiraishi2, K.
|
|
1
NTT Basic Research Laboratories, NTT Corporation, Japan
2 Institute of Physics, University of Tsukuba,
Japan |
|
|
P16
|
The
Evolution of the Resistance and Current Density During Electromigration
Ceric1,
H., Sabelka1, R., Holzer2, S., Wessner1,
W., Wagner2, S., Grasser2, T., Selberherr1,
S.
|
|
1
Christian Doppler Laboratory for TCAD in Microelectronics at the
Institute for Microelectronics
2 Institute for Microelectronics, TU Vienna,
Austria |
|
|
P17
|
3-D
Physically-Based Electromigration Simulation in Copper-Low-K
Interconnect
Sukharev,
V., Choudhury, R., Park, C. W.
|
|
LSI
Logic Corporation, Advanced Development, Milpitas, USA |
|
|
P18
|
3D
Feature-Scale Simulation of Sputter Etching with Coupling to Equipment
Simulation
Bär,
E., Lorenz, J., Ryssel, H.
|
|
Fraunhofer
Institute of Integrated Systems and Device Technology, Erlangen, Germany |
|
|
P19
|
Automatic
Optimization Algorithm for a Direct 2D and 3D Mesh Generation from the
Layout Information
Gnani,
E., Ghidoni, F., Rudan, M.
|
|
E.
De Castro Advanced Research Center on Electronic Systems (ARCES), and
Department of Electronics, Computer Science and Systems (DEIS),
University of Bologna, Italy |
|
|
P20
|
Genetic
Algorithm for Optimization and Calibration in Process Simulation
Fühner,
T., Erdmann, A., Ortiz, C. J., Lorenz, J.
|
|
Fraunhofer
Institute of Integrated Systems and Device Technology, Erlangen, Germany |
|
|
P21
|
Performance
Evaluation of Linear Solvers Employed for Semiconductor Device
Simulation
Wagner1,
S., Grasser1, T., Selberherr2, S.
|
|
1
Christian Doppler Laboratory for TCAD in Microelectronics at the
Institute for Microelectronics
2 Institute for Microelectronics, TU Vienna,
Austria |
|
|
P22
|
An
Analysis of the Effect of Surrounding Gate Structure on Soft Error
Immunity
Matsuoka,
F., Sakuraba, H., Masuoka, F.
|
|
Research
Institute of Electrical Communication, Tohoku University, Japan |
|
|
P23
|
Analytical
Modeling of Ge and Si Double-Gated(DG) NFETs and the Effect of Process
Induced Variations (PIV) on Device Performance
Pethe1,
A., Krishnamohan1, T., Uchida1,2, K., Saraswat1,
K. C.
|
|
1
Department of Electrical Engineering, Stanford University, Stanford
2 Advanced LSI Technology Laboratory, Toshiba
Corp., Japan |
|
|
P24
|
Proposal
of physics-based compact model for nanoscale MOSFETs including the
transition from drift-diffusion to ballistic transport
Mugnaini1,
G., Iannaccone1,2, G.
|
|
1
Dipartimento di Ingegneria dell’Informazione, Università di
Pisa, and
2 IEIIT-CNR, Pisa, Italy |
|
|
P25
|
A
New Methodology for Efficient and Reliable Large-Signal Analysis of RF
Power Devices
Ito1,
C., Tornblad2, O., Ma3, G., Dutton1,
R. W.
|
|
1 Center for Integrated
Systems, Stanford University, Stanford, CA USA
2 Infineon
Technologies North America Corp., Morgan Hill, CA USA
3 Infineon
Technologies North America Corp., Tempe, AZ USA
|
|
|
P26
|
Small-Signal
Modeling of RF CMOS
Jang1,
J., Dutton2, R. W.
|
|
1
Cypress Semiconductor, San Jose, USA
2 Center for Integrated System, Stanford
University, Stanford, USA |
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