The 2003 International Conference on simulation of Semiconductor Processes and Devices (SISPAD '03) will be held on September 3-5, 2003 at Boston Marriott Cambridge, Boston, Massachusetts.

Program for: September 4, 2003, Poster Session
             September 5, 2003

September 2, 6:00pm - 8:00pm
September 3, 7:30am - 2:00pm

Wednesday, September 3
8:30 - 8:45

Opening Remarks
Paco Leon, MT Associates


8:45 - 9:30
"Modeling and Characterization of Copper Interconnects for SoC Design"
N. D. Arora, Cadence Design Systems
9:30 - 10:15
"Experimental Studies of Dopant Diffusion in Strained Si and SiGe"
A. N. Larsen and N. Zangenberg, University of Aarhus, Aarhus, Denmark
Break (15 minutes)

10:30 - 11:15
"Experimental Study on Carrier Transport Mechanism in Ultra-thin Body SOI MOSFETs"
K. Uchida, H. Watanabe, J. Koga, A. Kinoshita and S. Takagi, TOSHIBA Corporation, Yokohama, Japan
11:15 - 12:00
"Quantum-dot Cellular Automata: An Architecture for Molecular Computing"
E. P. Blair and C. Lent, University of Notre Dame, Notre Dame, IN

Session 1 - Interconnect and Back End

1:30 - 1:55

"Microstructure Development and Evolution"
M. O. Bloomfield, Y. H. Im, T. S. Cale, Rensselaer Polytechnic Institute, Troy, NY
1:55 - 2:20
"CLIMATE (Chip-Level Intertwined Metal and Active Temperature Estimator)"
A. Labun, T. Reeve*, Hewlett-Packard, Shrewsbury, MA and *Intel, Shrewsbury, MA
2:20 - 2:45
"Scaling Laws for the Resistivity Increase of Sub-100nm Interconnects"
W. Steinhogl , G. Schindler, G. Steinlesberger, M. Traving, M. Engelhardt, Infineon Technologies AG, Munich, Germany
Break (15 minutes)
3:00 - 3:25
"Non Destructive Inverse-Modeling of Copper Interconnect Structure for 90nm Technology Node"
T. Kunikiyo, T. Watanabe, T. Kanamoto, H. Asazato, M. Shirota, K. Eikyu, Y. Ajioka, H. Makino, K. Ishikawa, S. Iwade, Y. Inoue, K. Yamashita*, M. Kobayashi*, A. Gohda*, Y. Oda*, R. Yamaguchi*, H. Umimoto*, K. Ohtani*, Mitsubishi Electric Corp., Itami, Japan and *Matsushita Electric Industrial Co., Ltd., Kyoto, Japan
3:25 - 3:50
"A Simple Wide-Band On-Chip Inductor Model for Silicon-Based RF IC's"
J. Gil, H. Shin, KAIST, Daejeon, Korea
3:50 - 4:15
"A Novel Technique for Full-wave Modeling of Large-scale Three-dimensional High-speed On/Off-chip Interconnect Structures"
D. Jiao, M. Mazumder, S. Chakravarty, C. Dai, M. J. Kobrinsky, M. C. Harmes, S. List, Intel Corp., Santa Clara, CA
4:15 - 4:40
"Photoresist Flow Simulation Using the Viscous Flow Model"
W.-Y. Chung, T.-K. Kim, Y.-T. Kim, B.-J. Hwang, B.-Y. Hwang, Y.-K. Park, J.-T Kong, Samsung Electronics Co. Ltd, Kyunggi-Do, Korea

Session 2 - Mobility and Transport Models

1:30 - 1:55

"A New Remote Coulomb Scattering Model for Ultrathin Oxide MOSFETs"
F. Gamiz, A. Godoy, J. B. Roldan, Universidad de Granada, Granada, Spain
1:55 - 2:20
"Mobility in UTB-SOI PFETS: Local Coordinate-Based Modeling with the Density Gradient Method"
D. Connelly, D. E. Grupp, P. Leon*, D. Yergeau*, Acorn Technologies, Palo Alto, CA and *Mixed Technology Associates, Palo Alto, CA
2:20 - 2:45
"Substrate Orientation-Dependence of Electron Mobility in Strained SiGe Layers"
S. Smirnov, H. Kosina, S. Selberherr, TU Vienna, Vienna, Austria
Break (15 minutes)
"Topography and Schottky-Contact Models Applied to NiSi SALICIDE Process"
N. Kusunoki, K. Ohuchi, A. Hokazono, H. Tanimoto, K. Matsuzawa, Toshiba Corporation, Yokohama, Japan
3:25 - 3:50
"Reformulation of Macroscopic Transport Models Based on the Moments of the Scattering Integral"
T. Grasser, H. Kosina, S. Selberherr, TU Vienna, Vienna, Austria
3:50 - 4:15
"Analysis of Gate Currents Through High-K Dielectrics using a Monte Carlo Device Simulator"
Y. Ohkura, C. Suzuki, H. Amakawa, K. Nishi, Semiconductor Leading Edge Technologies, Inc., Tsukuba, Japan
4:15 - 4:40
"Calibration of Hole Scattering Rates in Silicon with a Large Set of Experimental Data including High Voltage Quantum Yield, Drain Disturb and Substrate Hole Injection"
A. Ghetti, STMicroeletronics, Agrate Brianza, Italy
6:00 - 10:00pm Dinner at the Museum of Science