Conference Program

Wednesday 5 September 2001




SISPAD 2001 Opening


SESSION 1: Plenary Aristotelis Hall

(Chairperson: S. Selberherr)



Macroscopic Quantum Carrier Transport Modeling (Invited)

Zhiping Yu, R. W. Dutton, and Daniel W. Yergeau

Center for Integrated Systems, Stanford University, USA


Atomistic Front-End Process Modelling: A Powerful Tool for Deep- Submicron Device Fabrication (Invited)

M. Jaraiz, P. Castrillo, R. Pinacho, I. Martin-Bragado, and J. Barbolla

Dept. de Electronica, Univ. of Valladolid, Spain


Coffee Break


SESSION 2: Process Modeling I  Aristotelis Hall

(Chairperson: S. Dunham)



Monte Carlo Impurity Diffusion Simulation Considering Charged Species

Masami Hane1, Takeo Ikezawa1 and George H. Gilmer2

1Silicon Systems Research Laboratories, NEC Corporation, Japan

2Agere Systems, USA


A Novel Model for Boron Diffusion in SiGe Strained Layers Based on a Kinetics Driven Ge-B Pairing Mechanism

D. Villanueva1, P. Moens1, K. Rajendran2 and W. Schoenmaker2

1Alcatel Microelectronics, Belgium

2IMEC, Belgium


The Role of Incomplete Interstitial-Vacancy Recombination on Silicon Amorphization

Luis A. Marqués, Lourdes Pelaz, Jesús Hernández and Juan Barbolla

Departamento de Electrónica, Universidad de Valladolid, Spain


Atomistic simulations of extrinsic defects evolution and transient enhanced diffusion in silicon

F. Cristiano1, B. Colombeau2, C. Bonafos2, J. Aussoleil2, G. Ben Assayag2

and A. Claverie2

1LAAS/CNRS, France



Initial Conditions for Transient Enhanced Diffusion: Beyond the  Plus-Factor Approach

G. Hobler1 and V. Moroz2

1Univ. of Technology Vienna, Austria

2Avant! Corporation, USA


SESSION 3 : Device: MC DeviceSimulation  Athina Hall

(Chairperson: N. Goldsman)



Local Iterative Monte Carlo investigation of the influence of electron-electron scattering on short channel Si-MOSFETs

J. Jakumeit1, U. Ravaioli2

1Institute for Algorithm and Scientific Computing (SCAI),

GMD-German National Research Center for Information Technology, Germany

2Beckman Institute, University of Illinois at UC, USA



Simplified Inelastic Acoustic-Phonon Hole Scattering Model for Silicon

F. M. Bufler, A. Schenk and W. Fichtner

Institut für Integrierte Systeme, ETH Zürich, Switzerland


An Impact Ionization Model Including Non-Maxwellian and Non-Parabolicity Effects

T. Grasser, H. Kosina and S. Selberherr

Institute for Microelectronics, TU Vienna, Austria


Density of States and Group Velocity Calculations for SiO2

E. Gnani, S. Reggiani, and M. Rudan

Dipartimento di Elettronica, Università di Bologna, Italy


Investigation of Spurious Velocity Overshoot Using Monte Carlo Data

T. Grasser, H. Kosina and S. Selberherr

Institute of Microelectronics, TU Vienna, Austria




SESSION 4: Process Modeling II - Aristotelis Hall

(Chairperson: N. Cowern)



Elasto-Plastic Modeling of Microelectronics Materials for Accurate Prediction of the Mechanical Stresses in Advanced Silicon Technologies

Vincent Senez and Thomas Hoffmann



A Unified Model of Dopant Diffusion in SiGe

Ardechir Pakfar1, 2, A. Poncet2, T. Schwartzmann1 and H. Jaouen1

1STMicroelectronics, France.

2LPM-INSA de Lyon, France


A Simple Modeling and Simulation of Complete Suppression of Boron Out-Diffusion in Si1-xGex by Carbon Insertion

K. Rajendran and W. Schoenmaker

STDI/TCAD Division, IMEC, Belgium


On the Effect of Local Electronic Stopping on Ion Implantation Profiles in Non-Crystalline Targets

A. Burenkov1, Y. Mu1, 2and H. Ryssel1

1Fraunhofer Institute of Integrated Circuits, Germany

2Physics Department, Shandong University, P.R.China


Dynamics of p+ polysilicon gate depletion due to the formation of boron compounds in TiSi2

F. G. Lau and W. Molzer

Infineon Technologies AG, Germany


SESSION 5: Device Modeling - Athina Hall

(Chairperson: K. De Meyer)



Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1 µm MOSFETs

S. Kaya1, A. R. Brown2, A. Asenov2, D. Magot2 and T. Linton3

1SEECS, Ohio University, USA

2Device Modelling Group, University of Glasgow, UK

3TCAD Division, Intel Corporation, USA


Quantum Corrections in 3-D Drift Diffusion Simulations of Decanano MOSFETs Using an Effective Potential

J. R. Watling1, A.R.Brown1, A. Asenov1 and D. K. Ferry2

1University of Glasgow, UK

2Arizona State University, USA


Finite Element Simulation of 2D Quantum Effects in Ultra Short Channel MOSFETs with High-K Dielectric Gates

A. Poncet, B. Vergnet and M. Mouis

Laboratoire de Physique de la Matiére, UMR-CNRS, France


Decananometer FDSOI Device Optimization including Random Variation

Daniel Connelly

Acorn Technologies, USA


Fully 2D quantum-mechanical simulation of nanoscale MOSFET's

A. Pirovano1, A. L. Lacaita1, and A. S. Spinelli2

1DEI, Politecnico di Milano, Italy

2Dip. di Scienze CCFFMM, Univ. dell’Insubria and INFM, Italy


Poster Session


Thursday 6 September 2001


SESSION 6: Plenary - Aristotelis Hall

(Chairperson: G. Wachutka)



Ab-initio Electrodynamic Modeling of On-Chip Back-End Structures (Invited)

W. Schoenmaker, P. Meuris, W. Magnus

IMEC, Belgium


Analysis of Hot-Carrier-Induced Oxide Degradation in MOSFETs by Means of Full-Band Monte Carlo Simulation (Invited)

Yoshinari Kamakura, Kazuaki Deguchi, and Kenji Taniguchi

Department of Electronics and Information Systems, Osaka University, Japan


Coffee Break


SESSION 7: Process Modeling III - Aristotelis Hall

(Chairperson: M. Hane)



Acceleration of Lattice Monte Carlo Simulations and Application to Diffusion/Clustering of As at High Concentrations

Scott T. Dunham and Zudian Qin

Department of Electrical Engineering, University of Washington, USA.


Interstitial Cluster Evolution and Transient Phenomena in Si-crystal

Antonino La Magna1, Salvo Coffa1, Sebania Libertino1, Matthias Strobel 1 and Luciano Colombo2


2Dipartimento di Fisica, Universitá di Cagliari and INFM, Italy


Monitoring Arsenic In-Situ Doping with Advanced Models for Poly-Silicon CVD

W. Pyka1, C. Heitzinger1, N. Tamaoki2, T. Takase2, T. Ohmine2  and S. Selberherr1

1Institute for Microelectronics, TU Vienna, Austria

2TOSHIBA Corporate R&D Center, Japan.


Equipment and Process Simulation of Compound Semiconductor MOCVD in the Production Scale Multiwafer Planetary Reactor

M. Dauelsberg1, M. Deufel1, M. Reinhold1, G. Strauch1, T. Bergunde2 1AIXTRON AG, Germany

2Ferdinand-Braun Institute, Germany


Numerical Simulation of Non-Equilibrium, Ultra-Rapid Heating of Si-thin films by Nanosecond-Pulse Excimer Laser

A. T. Voutsas1, H. Kisdarjono2, R. Solanki2 and A. Kumar3

1Sharp Laboratories of America, USA

2Oregon Graduate Institute of Science and Technology, USA

3Fluent Inc., USA


SESSION8: Device Modeling II - Athina Hall

(Chairperson: P. Oldiges)



2D Hierarchical Radio-Frequency Noise Modeling Based on a Langevin-Type Drift-Diffusion Model and Full-Band Monte-Carlo Generated Local Noise Sources

S. Decker, C. Jungemann, B. Neinhüs and B. Meinerzhagen

University of Bremen, ITEM, Germany.


Variance and Covariance Estimation in Stationary Monte Carlo Device Simulation

H. Kosina, M. Nedjalkov and S. Selberherr

Institute of Microelectronics, TU Vienna, Austria


Analysis of Gate Tunneling Current in MOS Structures using Quantum Mechanical Simulation

Matsuto Ogawa and Tanroku Miyoshi

Department of Electrical and Electronics Engineering,

Kobe University, Japan


2-D Self-Consistent Solution of Schrödinger Equation, Boltzmann Transport Equation, Poisson and Current-continuity Equation for MOSFET

Chung-Kuang Huang and Neil Goldsman

Department of Electrical Engineering, University of Maryland, USA


Boundary Condition Models for Terminal Current Fluctuations

M. Nedjalkov, T. Grasser, H. Kosina and S. Selberherr

Institute for Microelectronics, TU Vienna, Austria




SESSION 9:Plenary - Aristotelis Hall

(Chairperson: K. Nishi)


Electron velocity in sub-50 nm channel MOSFETs (Invited)

Dimitri A. Antoniadis, Ihsan J. Djomehri and Anthony Lochtefeld

Microsystems Technology Laboratories, Massachusetts Institute of  Technology, USA


3D Statistical Simulation of Intrinsic Fluctuations in Decanano MOSFETs Introduced by Discrete Dopants, Oxide Thickness Fluctuations and LER


Asen Asenov

Department of Electronics and Electrical Engineering, University of Glasgow, UK


Coffee Break


SESSION 10 Plasma - Athina Hall

(Chairperson: W. Molzer)



Modeling of Reactive Ion Etching for Si/SiO2 Systems

S. Hamaguchi and H. Ohta

Department of Fundamental Energy Science, Kyoto University, Japan


Simulation and Prediction of Aspect Ratio Dependent Phenomena during SiO2 and Si Feature Etching in Fluorocarbon Plasmas

G. Kokkoris1, 2, E. Gogolides1, and A.G. Boudouvis2

1Institute of Microelectronics, NCSR “Demokritos”, Greece

2 Department of Chemical Engineering, National Technical University of Athens, Greece


System Level Modeling of an Electrostatic Torsional Actuator

Robert Sattler1, Gerhard Wachutka1, Florian Plötz2 and Sebastian Hoffmann3

1Institute for Physics of Electrotechnology, Munich University of Technology, Germany

2Infineon Technologies AG, Germany

3Optical Communications and High Frequency Engineering




SESSION 11 Device Modeling III - Aristotelis Hall

(Chairperson: M. Profirescu)



Impact of Substrate Resistance on Drain Current Noise in MOSFETs

Jung-Suk Goo1, Simona Donati2, Chang-Hoon Choi1, Zhiping Yu1, Thomas H. Lee1 and Robert W. Dutton1

2Dipartimento di Elettronica, Politecnico Di Torino, Italy.


An Efficient Frequency-Domain Analysis Technique of MOSFET Operation

Kyu-Il Lee1, Jinsoo Kim1, Hyungsoon Shin2, Chanho Lee3,

Young June Park1 and Hong Shick Min1

1School of Electrical Engineering and Computer Science, Seoul National University, Korea

2Dept. of Information Electronics Engineering Ewha Womans University, Korea

3School of Electronic Engineering, Soongsil University, Korea


Modeling of Bias Dependent Fluctuations of Flicker Noise of MOSFETs

Ken’ichiro Sonoda1, Motoaki Tanizawa1, Katsumi Eikyu1, Kiyoshi Ishikawa1, Toshio Kumamoto2, Hiroyuki Kouno2,

and Masahide Inuishi1

1Mitsubishi Electric Corp., Japan

2ULSI Development Center, System LSI Div.


Conference Dinner


Friday 7 September 2001


SESSION 12 Plenary - Aristotelis Hall

(Chairperson: P. Leon)



Compact MOS Modeling for RF CMOS Circuit Simulation (Invited)

A.J. Scholten, R. van Langevelde, L.F. Tiemeijer, R.J. Havens, and D.B.M. Klaassen

Philips Research Laboratories, The Netherlands


Statistical Analysis of VLSI Using TCAD (Invited)

Naoyuki Shigyo

System LSI Design Division, Toshiba Corporation Semiconductor Company, Japan


Coffee Break


SESSION 13: Non-Si Devices - Athina Hal

(Chairperson: S. Jones)



Numerical Modeling of Impact-Ionization Effects on Gate-Lag Phenomena in GaAs MESFETs

A. Wakabayashi, Y. Mitani, D. Kasai and K. Horio

Faculty of Systems Engineering, Shibaura Institute of Technology, Japan


Monte Carlo simulation of multi-band carrier transport in semiconductor materials with complex unit cells

H-E. Nilsson1, A. Martinez2, M. Hjelm1,2, E. Bellotti3 and K. Brennan4

1Dept. of Information Technology and Media, Sweden

2Dept. of Electronics, Kungl. Tekniska Högskolan, Sweden

3Department of Electrical and Computer Engineering, Boston University, USA

4School of Electrical and Computer Engineering, Georgia Tech, USA


Modeling Semiconductor Carbon Nanotube Rectifying Heterojunctions

Gary Pennington and Neil Goldsman

Department of Electrical Engineering, University of Maryland, USA.


Simulation of Vertical CEO-FETs by a Coupled Solution of the Schrödinger Equation with a Hydrodynamic Transport Model

J. Höntschel1, R. Stenzel1, W. Klix2, F. Ertl3, T. Asperger3, R. A. Deutschmann3, M. Bichler3 and G. Abstreiter3

1University of Applied Sciences Dresden, Germany

2Dresden University of Technology, Germany

3Walter Schottky Institute, TU Munich, Germany


A Computational Efficient Method for HBT Intermodulation Distortions and Two-Tone Characteristics Simulation

Kuen-Yu Huang, Yiming Li, C. P. Lee, and S. M. Sze

Department of Electronics Engineering, National Chiao Tung University, Taiwan


SESSION 14: Compact Modeling-SOI : Aristotelis Hall

(Chairperson: S. Odanaka)



Modeling the Impact of Body-to-body Leakage in  Partially-Depleted SOI CMOS Technology

MeiKei Ieong1, Ralph Young1, Heemyong Park1, Werner Rausch1, Isabel Yang1, Samuel Fung1, Fariborz Assaderaghi2

and H-S Philip Wong2


2IBM T.J. Watson Research Center, USA


Compact device model for partially depleted SOI-MOSFETs

Y. Fujii, R. Yoshimura, T. Matsuoka and K. Taniguchi

Department of Electronic and Information Systems, Graduate School of Engineering, Osaka University, Japan


Two-Dimensional Model for the Subthreshold Slope in Deep-Submicron Fully-Depleted SOI MOSFET's

Hans van Meer and Kristin De Meyer

STDI division, IMEC, Belgium

ESAT, K.U. Leuven, Belgium


3D Thermal Analysis for SOI and its impact on Circuit Performance

R.V. Joshi1, S.S. Kang2, and C.T. Chuang1

1IBM, T.J.Watson Res. Center, USA



Modelling of High-Voltage SOI-LDMOS Transistors including Self-Heating

A. C. T. Aarts1, M. J. Swanenberg2and W.J. Kloosterman2

1Philips Research Laboratories, The Netherlands

2Philips Semiconductors, The Netherlands




SESSION 15: Interconnects and MEMS - Aristotelis Hall

(Chairperson: W. Shoemmaker)



An Efficient Tool For Extraction of Interconnect Models in Submicron Layouts

P. Maffezzoni, A. Brambilla and A. L. Lacaita

DEI, Politecnico di Milano, Italy


A Comparative Study of Two Numerical Techniques for Inductance Calculation in Interconnect Structures

C. Harlander, R. Sabelka and S. Selberherr

Institute of Microelectronics, TU Vienna, Austria


Comparison of finite element stress simulation with X-ray measurement for the aluminum conductors with different passivation topography

Tai-Kyung Kim, Young-Pil Kim, Won-Young Chung, Young-Kwan Park and Jeong-Taek Kong

Semiconductor R&D Center, Samsung Electronics Co., Korea




SESSION16: Memory Devices - Athina Hall

(Chairpeson: H. Jaouen)


A New Compact Spice-like Model of E2PROM Memory Cells Suitable for DC and Transient Simulations

L. Larcher1, P. Pavan1, M. Cuozzo2 and A. Marmiroli2

1 D.S.I. and INFM, Universitá di Modena e Reggio Emilia, Italy

2STMicroelectronics, Italy


Simulation of Flash Memory Programming Characteristics

K. Matsuzawa and T. Ishihara

Advanced LSI Technology Laboratory, Toshiba Corporation, Japan


A Figure of Merit for Flash Memory Multi-Layer Tunnel Dielectrics

B. Govoreanu1, 2, P. Blomme1, 2, M. Rosmeulen1,2, J. Van Houdt1 and K. De Meyer1,2

1STDI Division, IMEC Leuven, Belgium

2ESAT, KU Leuven, Belgium


Coffee Break


SESSION 17: TCAD Application - Aristotelis Hall


(Chairperson: J. Lorenz)


Enhanced Diffusion of Phosphorus due to BPSG layer in SEG-MOSFETs

Jaehee Lee, Woo-Seock Cheong, Jae-Hoon Choi and Jae-Chul Om

Memory R&D Division, Hynix Semiconductor Inc., Korea


Neutron-SER Modeling & Simulation for 0.18µm CMOS Technology

Changhong Dai, Nagib Hakim, Steve Walstra, Scott Hareland, Jose Maiz, Scott Yu and Shiuh-Wuu Lee

Intel Corporation, USA


TCAD Driven Process Design of 0.15µm Fully-Depleted SOI Transistor for Low Power Applications

N. Miura, H. Hayashi, H. Komatsubara, M. Mochizuki, H. Matsuhashi, Y. Kajita and  K. Fukuda

VLSI Research Center, Oki Electric Industry Co., Japan


A Simulation Evaluation of 100nm CMOS Device Performance

S. K. Jones1, D. J. Bazley1, E. Augendre2, G. Badenes2, A. de Keersgieter2

and T. Skotnicki3

1 Caswell Technology, Marconi Optical Components, U.K

2IMEC, Belgium

3ST Microelectronics, France




SESSION 18: Modeling for Circuit Simulation - Athina Hall

(Chairperson: M. Miura-Mattausch)



A Practical Approach to Modeling Strained Silicon NMOS Devices

Phil Oldiges1, Xinlin Wang1, MeiKei Ieong1, Stephen Fischer1

and Ken Rim2


2 IBM T.J. Watson Research Center, USA


Accounting For Quantum Effects and Polysilicon Depletion in an Analytical Design-Oriented MOSFET Model

Matthias Bucher1, Jean-Michel Sallese2, Christophe Lallement3

1 National Technical University of Athens (NTUA), Greece

2 Swiss Federal Institute of Technology (EPFL), Switzerland

3 ERM-PHASE/ Ecole Nationale Supérieure de Physique de Strasbourg, France


Investigations of Salicided and Salicide-Blocked MOSFETs for ESD Including ESD Simulation

V. Axelrad1, Y. Huh2, J.W. Chen2 and P.Bendix2

1SEQUOIA Design Systems, USA

2LSI Logic Corp. USA


Bipolar Transistor's Intrinsic and Extrinsic Capacitance Determination

B. Ardouin, T. Zimmer, H. Mnif and P. Fouillat

Laboratoire de Microélectronique IXL, University of Bordeaux I, France


Conference Closing



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